Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
The S1C62740 has twin clock specification. The mask option
enables selection of either the CR or ceramic oscillation circuit
(OSC3 oscillation circuit) as the CPU's sub-clock. Because the
oscillation circuit itself is built-in, it provides the resistance as an
external element when CR oscillation is selected, but when ceramic
oscillation is selected both the ceramic oscillator and two capaci-
tors (gate and drain capacitance) are required.
Figure 4.3.3 is the block diagram of the OSC3 oscillation circuit.
OSC3 oscillation
circuit
(a) CR oscillation circuit
(b) Ceramic oscillation circuit
Fig. 4.3.3
OSC3 oscillation circuit
To CPU
(and serial interface)
Oscillation circuit
control signal
C
CR
OSC3
OSC4
R
CR
V
SS
C
GC
C
DC
Ceramic
OSC4
OSC3
R
R
DC
To CPU
(and serial interface)
Oscillation circuit
control signal
FC
As indicated in Figure 4.3.3, the CR oscillation circuit can be
configured simply by connecting the resistor (R
CR) between termi-
nals OSC3 and OSC4 when CR oscillation is selected. When 39 kΩ
is used for R
CR, the oscillation frequency is about 900 kHz. When
ceramic oscillation is selected, the ceramic oscillation circuit can
be configured by connecting the ceramic oscillator (Typ. 1 MHz)
between terminals OSC3 and OSC4 to the two capacitors (C
GC and
C
DC) located between terminals OSC3 and OSC4 and VSS. For both
C
GC and CDC, connect capacitors that are about 100 pF. To lower
current consumption of the OSC3 oscillation circuit, oscillation can
be stopped through the software.