Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
Control of watchdog
timer
Table 4.2.1 lists the watchdog timer's control bits and their ad-
dresses.
Table 4.2.1 Control bits of watchdog timer
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
The 1/2 Hz and 1/4 Hz data of the watchdog timer can be read
out. These bits are read only, and writing operations are invalid.
At initial reset, the watchdog timer data is initialized to "00B".
WD0, WD1:
Watchdog timer data
(E5H•D0, D1)
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
E2H
TMRST
W
0
0
0
TMRST
Reset
–
000
–
–
–
–
*2
*2
*2
*2
*5
*5
*5
*5
*7
Unused
Unused
Unused
Clock timer and watchdog timer reset
WD0
WDRST
0
WD1
WD0
Reset
–
0
0
Reset
–
WD10WDRST
E5H
*2
*5
*5
Watchdog timer reset
Unused
Watchdog timer data (1/4 Hz)
Watchdog timer data (1/2 Hz)
R
WR
WDRST:
Watchdog timer reset
(E5H•D3)
This is the bit for resetting the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset, and the
operation restarts immediately after this. When "0" is written to
WDRST, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
TMRST:
Clock timer reset
(E2H•D0)
This is the bit for resetting the clock timer and the watchdog timer.
When "1" is written: Clock timer and watchdog timer are reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to TMRST, the clock timer and the watchdog
timer are reset, and the operation restarts immediately after this.
When "0" is written to TMRST, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
Programming note
The watchdog timer must be reset within 3-second cycles. Because
of this, the watchdog timer data (WD0, WD1) cannot be used for
clocking of 3 seconds or more.