Specifications

I-20 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
Resetting Watchdog Timer4.2
Configuration of
watchdog timer
The S1C62740 incorporates a watchdog timer as the source oscilla-
tor for OSC1 (clock timer 1 Hz signal). The watchdog timer must be
reset cyclically by the software. If reset is not executed in at least
3–4 seconds, the initial reset signal is output automatically for the
CPU.
Figure 4.2.1 is the block diagram of the watchdog timer.
Fig. 4.2.1
Watchdog timer block diagram
Clock timer
TM0–TM7
1 Hz
Watchdog timer
WD0–WD1
Initial
reset signal
OSC1 demultiplier
(256 Hz)
Watchdog timer reset signal
Clock timer reset signal
The watchdog timer, configured of a two-bit binary counter (WD0,
WD1), generates the initial reset signal internally by overflow of the
WD1 (1/4 Hz).
Watchdog timer reset processing in the program's main routine
enables detection of program overrun, such as when the main
routine's watchdog timer processing is bypassed. Ordinarily this
routine is incorporated where periodic processing takes place, just
as for the timer interrupt routine.
The watchdog timer can also be reset by the resetting of the clock
timer.
The watchdog timer operates in the HALT mode. If the watchdog
timer is not reset within 3 or 4 seconds including the HALT status,
the IC reactivates from initial reset status.
The time during which oscillation is stopped due to the SLEEP
function is not included in the watchdog timer reset cycle.
When the SLEEP status has been cancelled and it has begun
oscillation, it successively restarts the count from the status at the
time oscillation stopped.