Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

II-90 EPSON S1C62740 TECHNICAL SOFTWARE
APPENDIX B: S1C62740 INSTRUCTION SET
Abbreviations used in the explanations have the following mean-
ings.
Symbols associated with
registers and memory
A ................ A register
B ................ B register
X ................ XHL register (low order eight bits of index register IX)
Y ................ YHL register (low order eight bits of index
register IY)
XH ............. XH register (high order four bits of XHL register)
XL .............. XL register (low order four bits of XHL register)
YH.............. YH register (high order four bits of YHL register)
YL .............. YL register (low order four bits of YHL register)
XP .............. XP register (high order four bits of index
register IX)
YP .............. YP register (high order four bits of index
register IY)
SP .............. Stack pointer SP
SPH............ High-order four bits of stack pointer SP
SPL ............ Low-order four bits of stack pointer SP
MX, M(X) .... Data memory whose address is specified with index
register IX
MY, M(Y)..... Data memory whose address is specified with index
register IY
Mn, M(n) .... Data memory address 000H–00FH (address specified
with immediate data n of 00H–0FH)
M(SP) ......... Data memory whose address is specified with stack
pointer SP
r, q ............. Two-bit register code
r, q is two-bit immediate data; according to the con-
tents of these bits, they indicate registers A, B, and
MX and MY (data memory whose addresses are
specified with index registers IX and IY)
rq
r1 r0 q1 q0
0000 A
0101 B
1010 MX
1111 MY
Registers specified