Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL SOFTWARE EPSON II-89
APPENDIX B: S1C62740 INSTRUCTION SET
Instruction set - 3
d3 d2, d2 d1, d1 d0, d0 C, C d3
d3 C, d2 d3, d1 d2, d0 d1, C d0
M(n3~n0) M(n3~n0)+1
M(n3~n0) M(n3~n0)-1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
5
0
0
0
1
1
1
1
r1
0
r1
0
1
r1
1
r1
0
r1
0
r1
1
r1
0
r1
0
1
0
1
1
1
1
1
1
r1
4
1
1
1
0
1
0
1
r0
0
r0
1
0
r0
1
r0
0
r0
1
r0
0
r0
0
r0
1
1
0
0
1
0
0
1
1
r0
3
1
1
1
0
0
0
0
i3
r1
i3
r1
r1
i3
r1
i3
r1
i3
r1
i3
r1
i3
r1
i3
r1
r1
1
n3
n3
1
1
1
1
1
2
0
0
0
0
0
1
1
i2
r0
i2
r0
r0
i2
r0
i2
r0
i2
r0
i2
r0
i2
r0
i2
r0
r0
1
n2
n2
0
1
0
1
1
1
0
0
1
r1
r1
r1
r1
i1
q1
i1
q1
q1
i1
q1
i1
q1
i1
q1
i1
q1
i1
q1
i1
q1
r1
r1
n1
n1
r1
r1
r1
r1
1
0
0
1
0
r0
r0
r0
r0
i0
q0
i0
q0
q0
i0
q0
i0
q0
i0
q0
i0
q0
i0
q0
i0
q0
r0
r0
n0
n0
r0
r0
r0
r0
1
YH
YL
F
SPH, r
SPL, r
r, SPH
r, SPL
r, i
r, q
r, i
r, q
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r
r
Mn
Mn
MX, r
MY, r
MX, r
MY, r
r
POP
LD
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
FAN
RLC
RRC
INC
DEC
ACPX
ACPY
SCPX
SCPY
NOT
Stack
operation
instructions
Arithmetic
instructions
Classification Operand
IDZC
↑↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
Clock
Operation Code Flag
YH
YL
F M(SP), SP SP+1
SPH
SPL
r SPH
r SPL
←
←
←
Mne-
monic
Operation
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↑
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
↓↓
★
★
★
★
★
★
★
★
★
★
★
r r+i3~i0
r r+q
r r+i3~i0+C
r r+q+C
r r-q
r r-i3~i0-C
r r-q-C
r r i3~i0
r r q
r r i3~i0
r r q
r r i3~i0
r r q
r-i3~i0
r-q
r i3~i0
r q
M(X) M(X)+r+C, X X+1
M(Y) M(Y)+r+C, Y Y+1
M(X) M(X)-r-C, X X+1
M(Y) M(Y)-r-C, Y Y+1
r r
M(SP), SP SP+1
M(SP), SP SP+1
←
←
←←
←
←
r
r
←←← ←
←← ← ←←
←
←
←
←
←
←
←
←
←
←
←