Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

II-88 EPSON S1C62740 TECHNICAL SOFTWARE
APPENDIX B: S1C62740 INSTRUCTION SET
Instruction set - 2
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
1
1
1
1
1
0
1
0
1
7
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
0
1
0
0
0
0
1
1
1
1
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
0
0
1
1
r1
0
1
1
0
0
1
1
1
1
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
0
1
r0
0
0
1
0
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
3
i3
i3
i3
i3
i3
r1
n3
n3
n3
n3
i3
r1
i3
r1
3
i3
i3
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
2
i2
i2
i2
i2
i2
r0
n2
n2
n2
n2
i2
r0
i2
r0
2
i2
i2
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
i1
i1
i1
i1
i1
q1
n1
n1
n1
n1
i1
q1
i1
q1
1
i1
i1
0
1
1
0
0
1
0
1
1
1
r1
0
0
1
1
0
0
1
r1
0
0
1
1
0
i0
i0
i0
i0
i0
q0
n0
n0
n0
n0
i0
q0
i0
q0
0
i0
i0
1
0
0
1
0
1
0
1
1
1
r0
0
1
0
1
0
1
0
r0
0
1
0
1
XH, i
XL, i
YH, i
YL, i
r, i
r, q
A, Mn
B, Mn
Mn, A
Mn, B
MX, i
r, q
MY, i
r, q
MX,
F, i
F, i
SP
SP
r
XP
XH
XL
YP
YH
YL
F
r
XP
XH
XL
YP
CP
LD
LDPX
LDPY
LBPX
SET
RST
SCF
RCF
SZF
RZF
SDF
RDF
EI
DI
INC
DEC
PUSH
POP
Index
operation
instructions
Data
transfer
instructions
Flag
operation
instructions
Stack
operation
instructions
Classification Operand
IDZC
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Clock
Operation Code Flag
XH-i3~i0
XL-i3~i0
YH-i3~i0
YL-i3~i0
r i3~i0
r q
A
B
M(n3~n0) A
M(n3~n0) B
M(X) i3~i0, X X+1
r q, X X+1
M(Y) i3~i0, Y Y+1
r q, Y Y+1
M(X) 3~ 0, M(X+1) 7~ 4, X X+2
←
←
F
F
C
C
Z
Z
D
D
I
I
←←
←
←
←←
←←
Mne-
monic
Operation
↓
↓
↓
↓
↑
↓
↑
↓
↓
↓
↓
↓
SP SP+1
SP SP-1
SP SP-1, M(SP) r
SP SP-1, M(SP) XP
SP SP-1, M(SP) XH
SP SP-1, M(SP) XL
SP SP-1, M(SP) YP
SP SP-1, M(SP) YH
SP SP-1, M(SP) YL
SP SP-1, M(SP) F
r M(SP), SP SP+1
XP
XH
XL
YP
←
←
M(n3~n0)
M(n3~n0)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
F i3~i0
F i3~i0
1
0
1
0
1 (Decimal Adjuster ON)
0 (Decimal Adjuster OFF)
1 (Enables Interrupt)
0 (Disables Interrupt)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←←
←
←
←
←
M(SP), SP SP+1
M(SP), SP SP+1
M(SP), SP SP+1
M(SP), SP SP+1
←
←
←
←
l llllllll l l l l