Specifications

I-12 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAMCHAPTER 3
3.1 CPU
The S1C62740 employs the 4-bit core CPU S1C6200A for the CPU,
so that register configuration, instructions and so forth are virtu-
ally identical to those in other family processors using the
S1C6200A.
Refer to "S1C6200/6200A Core CPU Manual" for details about the
S1C6200A.
Note the following points with regard to the S1C62740:
(1) Because the ROM capacity is 4,096 words, bank bits are unnec-
essary and PCB and NBP are not used.
(2) RAM is set up to three pages, so only the two low-order bits are
valid for the page portion (XP, YP) of the index register that
specifies addresses. (The two high-order bits are ignored.)
3.2 ROM
The built-in ROM, a mask ROM for loading the program, has a
capacity of 4,096 steps, 12 bits each. The program area is 16 pages
(0–15), each of 256 steps (00H–FFH). After initial reset, the pro-
gram beginning address is page 1, step 00H. The interrupt vector is
allocated to page 1, steps 02H–0FH.
Fig. 3.2.1
ROM configuration
Program start address
Interrupt vector address
0 page
00H step
01H step
02H step
0FH step
10H step
FFH step
12 bits
1 page
2 page
3 page
4 page
5 page
6 page
7 page
8 page
9 page
10 page
11 page
12 page
13 page
14 page
15 page
Program area