Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

II-86 EPSON S1C62740 TECHNICAL SOFTWARE
APPENDIX A: S1C62740 DATA MEMORY (RAM) MAP
Display memory (80H–9FH), I/O memory (C0H–FFH)
P
PROGRAM NAME:
H
L
0
1
2
8
9
C
D
E
F
NAME
MSB
LSB
NAME
MSB
LSB
NAME
MSB
LSB
NAME
MSB
LSB
NAME
MSB
LSB
NAME
MSB
LSB
0123456789ABCDEF
ZIPT
0
0
0
IPT
ZK0
K03
K02
K01
K00
ZBZCTL
BZR03
BZR02
0
BZFQ
ZGNDON
GNDON1
GNDON0
VRAON
VRON
ZISIO
0
0
0
ISIO
ZK1
0
0
0
K10
ZFOCTL
FOR00
0
FOFQ1
FOFQ0
ZAMPON
0
0
AMPON1
AMPON0
ZIK1
0
0
0
IK1
ZDFK0
DFK03
DFK02
DFK01
DFK00
ZTMRST
0
0
0
TMRST
ZAMPDT
0
0
AMPDT1
AMPDT0
ZIK0
0
0
0
IK0
ZDFK1
0
0
0
DFK10
ZTML
TM3
TM2
TM1
TM0
ZADRS
0
0
ADRS1
ADRS0
ZIAD
0
0
0
IAD
ZR0
R03
R02
R01
R00
ZTMH
TM7
TM6
TM5
TM4
ZAIS
AIS3
AIS2
AIS1
AIS0
ZISW
0
0
ISW1
ISW0
–
–
–
–
–
ZWDOG
WDRST
0
WD1
WD0
ZAI
AI3
AI2
AI1
AI0
ZIT
IT1
IT2
IT8
IT32
ZIOC
0
IOC2
IOC1
IOC0
ZSWCTL
0
0
SWRUN
SWRST
ZADON
ADON
0
0
AI4
–
–
–
–
–
ZPUP
0
PUP2
PUP1
PUP0
ZSWL
SWL3
SWL2
SWL1
SWL0
ZAD0
AD3
AD2
AD1
AD0
ZEIAD
0
EIAD
EISIO
EIPT
ZP0
P03
P02
P01
P00
ZSWH
SWH7
SWH6
SWH5
SWH4
ZAD1
AD7
AD6
AD5
AD4
ZEIK
0
0
EIK1
EIK0
ZP1
P13
P12
P11
P10
ZPTC1
PTR01
0
PTRUN
PTRST
ZAD2
AD11
AD10
AD9
AD8
ZSIK0
SIK03
SIK02
SIK01
SIK00
ZP2
P23
P22
P21
P20
ZPTC2
PTD1
PTD0
PTC1
PTC0
ZAD3
0
0
ADP
AD12
ZEISW
0
0
EISW1
EISW0
ZSIOC1
PFS
SDP
SCS1
SCS0
ZPTL
PT3
PT2
PT1
PT0
ZIDR
0
0
0
IDR
ZEIT
EIT1
EIT2
EIT8
EIT32
ZSIOC2
0
0
SCRUN
SCTRG
ZPTH
PT7
PT6
PT5
PT4
–
–
–
–
–
–
–
–
–
–
ZSDL
SD3
SD2
SD1
SD0
ZRDL
RD3
RD2
RD1
RD0
–
–
–
–
–
–
–
–
–
–
ZSDH
SD7
SD6
SD5
SD4
ZRDH
RD7
RD6
RD5
RD4
–
–
–
–
–
–
–
–
–
–
ZOSCC
0
0
CLKCHG
OSCC
ZLCDC
LDTY1
LDTY0
0
LCDON
ZSVDC
SVDS1
SCDS0
SVDDT
SVDON
3