Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-78 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
(2) When switching the clock from OSC3 to OSC1, use a separate
instruction for switching the OSC3 oscillation OFF. An error in
the CPU operation can result if this processing is performed at
the same time by the one instruction.
(3) To lessen current consumption, keep OSC3 oscillation OFF
except when the CPU must be run at high speed.
(4) When shifting to the SLEEP status, the CPU clock must be set
to OSC1 and the OSC3 oscillation circuit must be OFF.
Input ports When input ports are changed from low to high by pull up resistor,
the rise of the waveform is delayed on account of the time constant
of the pull up resistor and input gate capacitance. Hence, when
fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix
configuration.
Make this waiting time the amount of time or more calculated by
the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull up resistance 300 kΩ
Output ports (1) When BZ, BZ, FOUT and PTOVF output are selected by soft-
ware, a hazard may be observed in the output waveform when
the data of the output register changes.
(2) When R00 is used for general output port, set FOR00 to "0".
When R00 is used for FOUT output, set FOR00 to "1".
(3) When R01 is used for general output port, set PTR01 to "0".
When R01 is used for PTOVF output, set PTR01 to "1".
(4) When R02 is used for general output port, set BZR02 to "0".
When R02 is used for buzzer output, set BZR02 to "1".
(5) When R03 is used for general output port, set BZR03 to "0".
When R03 is used for buzzer inverted output, set BZR03 to "1".
I/O ports (1) When P20–P23 is used as general I/O ports, set PFS to "0".
(2) When P20–P23 is used as serial I/O ports, set PFS to "1".
(3) When in the input mode, I/O ports are changed from low to
high by pull up resistor, the rise of the waveform is delayed on
account of the time constant of the pull up resistor and input
gate capacitance. Hence, when fetching input ports, set an
appropriate wait time.
Particular care needs to be taken of the key scan during key
matrix configuration.