Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-77
CHAPTER 7: SUMMARY OF NOTES
7.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category.
Keep these notes well in mind when programming.
System initialization In some of initial registers and initial data memory area, the initial
value is undefined after reset. Set them proper initial values by the
program, as necessary.
Memory Memory is not mounted in unused area within the memory map
and in memory area not indicated in this manual. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these area.
SVD (Supply voltage
detection) circuit
(1) The SVD circuit should normally be turned OFF (SVDON = "0")
as the consumption current of the IC becomes large when it is
ON (SVDON = "1").
(2) To obtain a stable result, the SVD circuit must be set to ON
with at least 100 µsec. Hence, to obtain the SVD detection
result, follow the programming sequence below.
1. Set SVDON to "1" (ON)
2. Maintain at least 100 µsec minimum
3. Set SVDON to "0" (OFF)
4. Read out SVDDT
However, when a crystal oscillation clock (f
OSC1) is selected for
CPU system clock, the instruction cycle are long enough, so
that there is no need for concern about maintaining 100 µsec
for the SVDON = "1" with the software.
Watchdog timer (1) The watchdog timer must be reset within 3-second cycles.
Because of this, the watchdog timer data (WD0, WD1) cannot be
used for clocking of 3 seconds or more.
(2) When clock timer resetting (TMRST ← "1") is performed, the
watchdog timer is also reset.
Oscillation circuit (1) It takes at least 5 msec from the time the OSC3 oscillation
circuit goes ON until the oscillation stabilizes. Consequently,
when switching the CPU operation clock from OSC1 to OSC3,
do this after a minimum of 5 msec have elapsed since the OSC3
oscillation went ON.
Further, the oscillation stabilization time varies depending on
the external oscillator characteristics and conditions of use, so
allow ample margin when setting the wait time.