Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-71
CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt)
Table 6.15.2 Interrupt flags and interrupt mask registers
Example program
for the interrupt
Following program shows the interrupt procedure.
Label Mnemonic/operand Comment
Interrupt factor Interrupt factor flag Interrupt mask register
Falling edge of clock timer (1 Hz) IT1 (C6H•D3) EIT1 (CCH•D3)
Falling edge of clock timer (2 Hz) IT2 (C6H•D2) EIT2 (CCH•D2)
Falling edge of clock timer (8 Hz) IT8 (C6H•D1) EIT8 (CCH•D1)
Falling edge of clock timer (32 Hz) IT32 (C6H•D0) EIT32 (CCH•D0)
Falling edge of stopwatch timer (1 Hz) ISW1 (C5H•D1) EISW1 (CBH•D1)
Falling edge of stopwatch timer (10 Hz) ISW0 (C5H•D0) EISW0 (CBH•D0)
A/D converter converting finish IAD (C4H•D0) EIAD (C8H•D2)
No matching between input ports (K00–K03) IK0 (C3H•D0) EIK0 (C9H•D0)
and input comparison registers (DFK00–DFK03) SIK00 (CAH•D0)
SIK01 (CAH•D1)
SIK02 (CAH•D2)
SIK03 (CAH•D3)
No matching between input port K10 IK1 (C2H•D0) EIK1 (C9H•D1)
and input comparison register DFK10
Data (8 bits) input/output of ISIO (C1H•D0) EISIO (C8H•D1)
serial interface has completed
Programmable timer down count to 00H IPT (C0H•D0) EIPT (C8H•D0)
;*
;* INTERRUPT
;*
ZIPT EQU 0C0H ;PTM INTERRUPT FACTOR FLAG
ZISIO EQU 0C1H ;SIO INTERRUPT FACTOR FLAG
ZIK1 EQU 0C2H ;K10 INTERRUPT FACTOR FLAG
ZIK0 EQU 0C3H ;K00-K03 INTERRUPT FACTOR FLAG
ZIAD EQU 0C4H ; A/D CONVERTER INTERRUPT FACTOR FLAG
ZISW EQU 0C5H ;STW INTERRUPT FACTOR FLAG
ZIT EQU 0C6H ;TIMER INTERRUPT FACTOR FLAG
ZWDOG EQU 0E5H ;WATCHDOG REGISTER
;
ORG 102H
JP TMINT ;TIMER (7th PRIORITY)
;
ORG 104H
JP SWINT ;STOPWATCH (6th PRIORITY)
;
ORG 106H
JP ADINT ;A/D (5th PRIORITY)
;
ORG 108H
JP K0INT ;K0 (4th PRIORITY)
;
ORG 10AH
JP K1INT ;K10 (3rd PRIORITY)