Specifications

S1C62740 TECHNICAL SOFTWARE EPSON II-69
CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt)
Interrupt6.15
Interrupt vector,
factor flag, and
mask register
When an interrupt request is issued to the CPU, the CPU starts
interrupt processing.
Interrupt processing is accomplished by the following steps after
the instruction being executed is completed.
➀ The address (value of the program counter) of the program
which should be run next is saved in the stack area (RAM).
➁ The vector address (1 page 02H–0FH) for each interrupt request
is set to the program counter.
➂ Branch instruction written to the vector is effected (branch to
software interrupt processing routine).
Note: Time equivalent to 12 cycles of CPU system clock is required for steps ➀
and ➁ .
The interrupt request and interrupt vector correspondence is
shown in Table 6.15.1.
Interrupt vector
(PCP and PCS)
102H Clock timer interrupt Low
104H Stopwatch timer interrupt ↑
106H A/D converter interrupt
108H Input (K00–K03) interrupt
10AH Input (K10) interrupt
10CH Serial interface interrupt ↓
10EH Programmable timer interrupt High
Interrupt request Priority
When multiple interrupts simultaneously occur, the high priority
vector address is set to the program counter.
The interrupt factor flags and interrupt mask registers correspond-
ence are shown in Table 6.15.2.
The configuration of the interrupt circuit is shown in Figure 6.15.1.
Table 6.15.1
Interrupt request and interrupt
vectors