Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-62 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter)
A/D converter interrupt
When the reverse integration period has terminates, the A/D
interrupt factor flag IAD is set to "1" and an interrupt occurs.
The A/D interrupt can also be masked by writing a "0" into the
interrupt mask register EIAD. When EIAD is set to "1", an interrupt
occurs.
The interrupt factor flag IAD is set to "1" when the reverse integra-
tion period has terminates, regardless of the setting of the interrupt
mask register and is reset to "0" by reading.
Example program
for the A/D
converter
Following program shows the A/D converter controlling procedure.
Label Mnemonic/operand Comment
;*
;* A/D CONVERTER
;*
ZIAD EQU 0C4H ;A/D CONVERTER INTERRUPT FACTOR FLAG
ZEIAD EQU 0C8H ;A/D,SIO,PT INTERRUPT MASK REGISTER
ZGNDON EQU 0F0H ;GNDON1,GNDON0,VRAON,VRON
ZADRS EQU 0F3H ;A/D CONVERTER RESOLVING POWER
;/CONVERSION SPEED SELECTION
ZAIS EQU 0F4H ;A/D MODE SELECTION
ZAI EQU 0F5H ;A/D INPUT TERMINAL
ZADON EQU 0F6H ;A/D CONVERTER CLEAR AND ON/OFF
ZAD0 EQU 0F7H ;A/D CONVERTER COUNTER DATA 0 (LOWER)
ZAD1 EQU 0F8H ;A/D CONVERTER COUNTER DATA 1
ZAD2 EQU 0F9H ;A/D CONVERTER COUNTER DATA 2
ZAD3 EQU 0FAH ;A/D CONVERTER COUNTER DATA 3 (HIGHER)
ZIDR EQU 0FBH ;A/D CONVERTER READOUT VALID
;
DATA0 EQU 0H ;STORE A/D CONVERTER DATA
DATA1 EQU 1H
DATA2 EQU 2H
DATA3 EQU 3H
VALID EQU 4H ;STORE THE VALID FLAG
;
ORG 106H
JP ADINT ;A/D INTERRUPT ROUTINE
;
INITAD:
LD X,ZGNDON ;GND AND VR SIGNAL OFFER
;BY EXTERNAL CIRCUIT
LD MX,0000B
;
LD X,ZADRS ;SET CONVERSION SPEED = 500 mS
LD MX,0
;
LD X,ZAIS ;SET FOR MEASUREMENT TERMINAL
;VOLTAGE VS GND