Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-58 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (SVD Circuit)
Example program
for the SVD circuit
Following program shows the SVD controlling procedure.
Label Mnemonic/operand Comment
;*
;* SVD (FOR OSC1 OPERATION)
;*
ZSVDC EQU 0FFH ;SVD CONTROL REGISTER
;
SCDCHK:
LD X,ZSVDC
LD MX,0000B ;SET CRITERIA VOLTAGE = 2.6 V
;
OR MX,0001B ;START CHECK SUPPLY VOLTAGE
AND MX,1110B ;TURN OFF SVD
;
LD A,MX ;READ SVD DATA INTO A REGISTER'S BIT 1
RET
;
Programming notes
(1) The SVD circuit should normally be turned OFF (SVDON = "0")
as the consumption current of the IC becomes large when it is
ON (SVDON = "1").
(2) To obtain a stable result, the SVD circuit must be set to ON
with at least 100 µsec. Hence, to obtain the SVD detection
result, follow the programming sequence below.
1. Set SVDON to "1" (ON)
2. Maintain at least 100 µsec minimum
3. Set SVDON to "0" (OFF)
4. Read out SVDDT
However, when a crystal oscillation clock (f
OSC1) is selected for
CPU system clock, the instruction cycle are long enough, so
that there is no need for concern about maintaining 100 µsec
for the SVDON = "1" with the software.