Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
The GND (ground) explained here following becomes the standard
for both V
R1 and VR2 and becomes the electric potential of the VSS
side.
Refer to the section "A/D Converter" for details such as circuit
configuration.
Note: Since the built-in reference voltage generation circuit is under develop-
ment, the reference voltage should be impressed from outside.
Reference voltage
<GND> for analog
circuit
Since GND becomes the standard for the analog input voltage that
performs the A/D conversion, inside the circuit it is obtained by
voltage dividing the power voltage impressed between the V
DDA–
V
SSA terminals to about 1/2 by means of a resistance.
In addition, the GND (ground) level can also be impressed exter-
nally.
Initial Reset
To initialize the S1C62740 circuits, initial reset must be executed.
There are three ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous low input to terminals K00–K03
(3) Initial reset by watchdog timer
Be sure to use reset functions (1) when making the power and be
sure to initialize securely. In normal operation, the circuit may be
initialized by any of the above three types.
Figure 2.2.1 shows the configuration of the initial reset circuit.
2.2
Fig. 2.2.1
Configuration of the
initial reset circuit
RESET
K00
K01
K02
K03
OSC2
OSC1
OSC1
oscillation
circuit
Noise
reject
circuit
Initial
reset
Time
authorize
circuit
Clock timer Watchdog timer
V
DD
V
DD
Mask option
SLEEP
(In SLEEP mode: HIGH)