Specifications

II-54 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit)
Programming notes
(1) When using the serial interface in the master mode, the syn-
chronous clock uses the CPU system clock. Accordingly, do not
change the system clock (f
OSC1 ↔ fOSC3) while the serial inter-
face is operating.
(2) Perform data writing/reading to data registers SD0–SD7 only
while the serial interface is halted (i.e., the synchronous clock is
neither being input or output).
(3) As a trigger condition, it is required that data writing or reading
on data registers SD0–SD7 be performed prior to writing "1" to
SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed
in the RUN state. Moreover, when the synchronous clock SCLK
is external clock, start to input the external clock after the
trigger.
(4) Be sure that writing to the interrupt mask register is done with
the interrupt in the DI status (interrupt flag = "0"). Writing to
the interrupt mask register while in the EI status (interrupt flag
= "1") may cause malfunction.
(5) Read the interrupt factor flag in the DI status (interrupt flag =
"0"). Reading of interrupt factor flag is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the inter-
rupt factor flags to be read is set to "1", an interrupt request will
be generated by the interrupt factor flags set timing, or an
interrupt request will not be generated.
(6) SCTRG can be read or write. After write "1" to SCTRG, it will
still high until serial data been shift in or out completely.