Specifications

S1C62740 TECHNICAL SOFTWARE EPSON II-51
CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit)
The input data will be fetched at the rising edge of SCLK.
When the input of the 8 bits data from SD0–SD7 is completed, the
interrupt factor flag ISIO is set to "1" and interrupt is generated.
Moreover, the interrupt can be masked by the interrupt mask
register EISIO. Note, however, that regardless of the setting of the
interrupt mask register, the interrupt factor flag is set to "1" after
input of the 8 bits data.
Also, the data input in the shift register can be read from data
registers SD0–SD7 by software.
Example program
for the serial
interface circuit
Following program shows the serial interface controlling procedure.
Label Mnemonic/operand Comment
;*
;* SERIAL INTERFACE (SIO)
;*
ZISIO EQU 0C1H ;SIO INTERRUPT FACTOR FLAG
ZEIAD EQU 0C8H ;A/D,SIO,PTM INTERRUPT MASK REGISTER
ZK0 EQU 0D0H ;K0 INPUT PORT
;(SLAVE MACHINE'S NSRDY IS CONNECT
; TO MASTER MACHINE'S K00 FOR CHECK
; SLAVE MACHINE READY OR NOT)
ZSIOC1 EQU 0DBH ;SIO CONTROL REGISTER 1
ZSIOC2 EQU 0DCH ;SIO CONTROL REGISTER 2
ZSDL EQU 0DDH ;SERIAL INTERFACE DATA LOW
ZSDH EQU 0DEH ;SERIAL INTERFACE DATA HIGH
ZPTC1 EQU 0E9H ;PROGRAMMABLE TIMER CONTROL REGISTER 1
ZPTC2 EQU 0EAH ;PROGRAMMABLE TIMER CONTROL REGISTER 2
ZRDL EQU 0EDH ;PROGRAMMABLE TIMER RELOAD LOW
ZRDH EQU 0EEH ;PROGRAMMABLE TIMER RELOAD HIGH
;
SENDL EQU 00H ;SENDING DATA BUFFER FOR SDL
SENDH EQU 01H ;SENDING DATA BUFFER FOR SDH
;
ORG 10CH
;
Fig. 6.10.1
Serial interface timing chart
SCTRG
SCLK
SIN
8-bit shift register
SOUT
ISIO
SRDY (slave mode)
SRDY (master mode)
SCRUN
(high)