Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-8 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
VD1 is the voltage of the oscillation circuit and the internal logic
circuit, and is generated by the oscillation system regulated voltage
circuit for stabilizing the oscillation.
Making V
SS the standard (logic level 0), the oscillation system
regulated voltage circuit generates V
D1 from the supply voltage that
is input from the V
DD–VSS terminals.
Voltage <VD1> for
oscillation circuit
and internal circuit
Voltage <VC1, VC2
and VC3> for LCD
driving
VC1, VC2 and VC3 are the voltages for LCD drive, and are generated
by the LCD system regulated voltage circuit and the voltage booster
circuit to stabilize the display quality.
V
C1 is generated by the LCD system regulated voltage circuit with
V
SS as the standard from the supply voltage input from the VDD–
V
SS terminals.
V
C2 and VC3 are respectively double and triple obtained from the
voltage booster circuit.
The V
C1 voltage can be adjusted to match the LCD panel character-
istics by applying feedback to the V
CA terminal using resistances
RA1 and RA2 as shown in Figure 2.1.2.
The voltage V
C (≈VC1–VSS) of VC1 at this time is shown by the
following expression:
V
C ≈ 1 × (RA1 + RA2) / RA1
Example:
VC RA1 RA2
About 1 V ∞ 0 Ω
About 1.5 V 2 M 1 MΩ
See Chapter 7, "ELECTRICAL CHARAC-
TERISTICS" for voltage values.
+
–
V
C1
V
CA
RA2
RA1
V
SS
V
SS
+
–
V
C1
V
CA
V
SS
V
C
= 1.5 V V
C
= 1 V
(1 M )Ω
(2 M )Ω
Fig. 2.1.2
VC Adjustment circuit
VR1 and VR2 are the reference voltage of the A/D converter. VR1 is
generated by the regulated voltage circuit and V
R2 by resistance
splitting of V
R1. VR1 and VR2 may also be adjusted from outside.
Use of the external adjustment or the internal adjustment can be
selected by the mask option. In addition, it is possible to impress
V
R1 externally.
V
R1 is used to generate VR2 and the reference voltage during
resistance measurement using an A/D converter and V
R2 becomes
the reference voltage at the time of voltage measurement by the A/
D converter.
Reference voltage
<VR1 and VR2> for
A/D converter