Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-46 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer)
Overflow signal output
Overflow signal of programmable timer is generated to output port
R01 if RTR01 is set. This overflow output is toggled when program-
mable timer completes the down-counting (at the same time reload
occurs).
PTRST
PTRUN
Timer data
R01
Timer overflow (reload)
Fig. 6.9.3
Programmable timer
overflow output
(PTR01 = "1", R01 register = "0")
Note: When R01 output port is set for PTOVF, set R01 to "0".
Example program
for the
programmable timer
Following program shows the programmable timer controlling
procedure.
Label Mnemonic/operand Comment
;*
;* PROGRAMMABLE TIMER (PT)
;*
ZIPT EQU 0C0H ;PROGRAMMABLE TIMER INTERRUPT FACTOR FLAG
ZEIAD EQU 0C8H ;A/D, SIO, PTM INTERRUPT MASK REGISTER
ZPTC1 EQU 0E9H ;PROGRAMMABLE TIMER CONTROL REGISTER 1
ZPTC2 EQU 0EAH ;PROGRAMMABLE TIMER CONTROL REGISTER 2
ZPTL EQU 0EBH ;PROGRAMMABLE TIMER DATA LOW NIBBLE
ZPTH EQU 0ECH ;PROGRAMMABLE TIMER DATA HIGH
ZRDL EQU 0EDH ;PROGRAMMABLE TIMER RELOAD LOW
ZRDH EQU 0EEH ;PROGRAMMABLE TIMER RELOAD HIGH
ZR0 EQU 0D4H ;R0 OUTPUT PORT
;
ORG 10EH
JP PTINT ;PT INTERRUPT SERVICE ROUTINE
;
PTINIT:
;* ENABLE INTERRUPT FOR PT, RESET AND START IT.
;
DI
LD X,ZIPT;RESET PT INTERRUPT FLAG
LD A,MX
LD X,ZEIAD ;ENABLE PT INTERRUPT
OR MX,0001B
;
LD X,ZRDL;SET RELOAD REGISTER AS 00H
LBPX MX,00H;(RDL,RDH) = (0,0)
;
LD ZR0