Specifications

II-44 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer)
S1C62740 has a programmable timer with OSC1, OSC3 and
external K10 input predivided.
Input clock selection
Input clock may be selected by PTC1 and PTC0 as shown in Table
6.9.2.
Control of the
programmable timer
PTC1 PTC0 Input clock
0 0 K10 input with noise rejector (256 Hz)
0 1 K10 input direct
10f
OSC1 (32 kHz)
11f
OSC3 (1 MHz)
Table 6.9.2
Programmable timer input clock
selection
In case of K10 input, the down count timing becomes the falling
edge of the clock and in f
OSC1 and fOSC3 it becomes the rising edge.
K10 input
f
OSC1
f OSC3
Down count
External clock of K10 input (with noise rejector) is for counting by
key entry, the input signal from which passes the 256 Hz sampling
noise reject circuit. With this, no more than 2 msec of chattering is
purged, and at least 6 msec signal is received. (Acceptance of
signals within the range from 2 msec to 6 msec is uncertain.)
Input clock predivided selection
The input clock is predivided by the dividing ratio selection regis-
ters PTD1 and PDT0 setting as shown in Table 6.9.3.
Fig. 6.9.1
Timing of down-counts
(predivider = 1/1)
PTC1 PTC0 Dividing ratio
0 0 1/256
0 1 1/32
10 1/4
11 1/1
Table 6.9.3
Programmable timer input clock
predivided selection
Setting of initial value
The initial value of count data can be set by software to the reload
registers RD0–RD7; at the point where the down-counter value is
"0", the programmable timer reloads the initial value and continues
to down-count.