Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-43
CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer)
Programmable Timer6.9
I/O data memory of
the programmable
timer
The control registers of the programmable timer are shown in Table
6.9.1.
Table 6.9.1 Control registers of programmable timer
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
C0H
IPT
R
0
0
0
IPT
–
–
–
0
Unused
Unused
Unused
Interrupt factor flag (programmable timer)
Yes No
000
*2
*2
*2
*5
*5
*5
*4
C8H
EIPT
0
EIAD
EISIO
EIPT
–
0
0
0
Unused
Interrupt mask register (A/D converter)
Interrupt mask register (serial interface)
Interrupt mask register (programmable timer)
Enable
Enable
Enable
Mask
Mask
Mask
EISIOEIAD0
*2
*5
*7
R/WR
E9H
PTRST
W
PTR01
0
PTRUN
PTRST
0
–
0
–
R01 port output selection
Unused
Programmable timer Run/Stop
Programmable timer reset (reload)
PTOVF
Run
Reset
DC
Stop
–
PTRUN
R/W
0
R
PTR01
R/W
*2
*2
*5
*5
EAH
PTC0
PTD1
PTD0
PTC1
PTC0
0
0
0
0
PTC1PTD0PTD1
R/W
EBH
PT0
R
PT3
PT2
PT1
PT0
–
–
–
–
PT1PT3
*3
*3
*3
*3
ECH
PT4
PT7
PT6
PT5
PT4
–
–
–
–
PT5PT6PT7
*3
*3
*3
*3
Programmable timer pre-divider selection
0: 1/256, 1: 1/32, 2: 1/4, 3: 1/1
Programmable timer clock source selection
0: K10 (NR), 1: K10, 2: f
OSC1, 3: fOSC3
R
PT2
EDH
RD0
RD3
RD2
RD1
RD0
–
–
–
–
RD1RD2RD3
R/W
EEH
RD4
RD7
RD6
RD5
RD4
–
–
–
–
RD5RD6RD7
R/W
*3
*3
*3
*3
*3
*3
*3
*3
Programmable timer reload data
(low-order 4 bits)
LSB
Programmable timer reload data
(high-order 4 bits)
MSB
Programmable timer data (low-order 4 bits)
LSB
Programmable timer data (high-order 4 bits)
MSB