Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-40 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Stopwatch Timer)
Stopwatch timer interrupt
The stopwatch timer interrupt is generated at the falling edge of the
frequencies (10 Hz and 1 Hz). At this time, the corresponding
interrupt factor flag (ISW0 and ISW1) is set to "1".
Selection of whether to mask the separate interrupts can be made
with the interrupt mask registers (EISW0 and EISW1). However,
regardless of the interrupt mask register setting, the interrupt
factor flag is set to "1" at the falling edge of the corresponding
signal.
Figure 6.8.1 shows the operation of the stopwatch timer.
Example program
for the stopwatch
timer
Following program shows the stopwatch timer controlling proce-
dure.
Label Mnemonic/operand Comment
;*
;* STOPWATCH TIMER
;*
ZISW EQU 0C5H ;STOPWATCH INTERRUPT FACTOR FLAG
ZEISW EQU 0CBH ;STOPWATCH INTERRUPT MASK REGISTER
ZSWCTL EQU 0E6H ;STOPWATCH CONTROL REGISTER
ZSWL EQU 0E7H ;STOPWATCH TIMER DATA LOW
ZSWH EQU 0E8H ;STOPWATCH TIMER DATA HIGH
;
ORG 104H
JP SWINT ;STOPWATCH INTERRUPT ROUTINE
;
Fig. 6.8.1
Stopwatch timer operating timing
Address
Address
Register
Register
Stopwatch timer (SWL) timing chart
Stopwatch timer (SWH) timing chart
10 Hz interrupt request
1 Hz interrupt request
E8H
E7H
D0
D1
D2
D3
D0
D1
D2
D3
(1/100 sec BCD)
(1/10 sec BCD)