Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-38 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer)
LD A,MX
;
LD X,ZEIT ;SET TO TIMER MASK REGISTER
LD MX,0100B ;ENABLE TIMER 2 Hz INTERRUPT
EI
RET
;
;* CLOCK TIMER INTERRUPT
;
TMINT:
LD X,ZIT ;LOAD TIMER INTERRUPT FLAG
;TO B REGISTER
LD B,MX
FAN B,0100B ;CHECK TIMER 2 Hz INTERRUPT FLAG
JP Z,TMINT1 ;NO, THEN JMP
LD X,ZTML ;SET TO TIMER DATA ADDRESS
LDPX A,MX ;READ TIMER LOW INTO A REGISTER
LD B,MX ;READ TIMER HIGH INTO B REGISTER
;:
; DO THE PROCEDURE FOR 2 Hz INTERRUPT SERVICE
;:
TMINT1:
EI
RET
;
(1) Be sure to data reading in the order of low-order data (TM0–
TM3) then high-order data (TM4–TM7).
(2) When the clock timer has been reset, the interrupt factor flag
(IT) may sometimes be set to "1". Consequently, perform flag
reading (reset the flag) as necessary at reset.
(3) When the clock timer has been reset, the watchdog timer is also
reset.
(4) Write the interrupt mask register (EIT) only in the DI status
(interrupt flag = "0"). Writing during EI status (interrupt flag =
"1") will cause malfunction.
(5) Reading of interrupt factor flags is available at EI, but be careful
in the following cases.
If the interrupt mask register value corresponding to the inter-
rupt factor flags to be read is set to "1", an interrupt request will
be generated by the interrupt factor flags set timing, or an
interrupt request will not be generated. Be very careful when
interrupt factor flags are in the same address.
Programming notes