Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-37
CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer)
However, regardless of the interrupt mask register setting, the
interrupt factor flag is set to "1" at the falling edge of the corre-
sponding signal.
Clock timer timing chart
FrequencyRegisterAddress
E4H
D3
D0
D1
D2
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
1 Hz interrupt request
E3H
2 Hz interrupt request
D3 1 Hz
D0
D1
D2
128 Hz
16 Hz
8 Hz
32 Hz
64 Hz
Fig. 6.7.1 Timing chart of clock timer
Following program shows the clock timer controlling procedure.
Label Mnemonic/operand Comment
Example program
for the clock timer
;*
;* CLOCK TIMER
;*
ZIT EQU 0C6H ;CLOCK TIMER INTERRUPT FACTOR FLAG
ZEIT EQU 0CCH ;CLOCK TIMER INTERRUPT MASK REGISTER
ZTMRST EQU 0E2H ;CLOCK TIMER RESET
ZTML EQU 0E3H ;CLOCK TIMER DATA LOW
ZTMH EQU 0E4H ;CLOCK TIMER DATA HIGH
;
ORG 102H
JP TMINT ;TIMER INTERRUPT ROUTINE
;
TMINIT:
LD X,ZTMRST ;RESET CLOCK TIMER
OR MX,0001B
;
DI
LD X,ZIT ;RESET IT FLAGS