Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-36 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer)
Clock Timer6.7
I/O data memory of
the clock timer
The control registers of the clock timer are shown in Table 6.7.1.
Table 6.7.1 Control registers of clock timer
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Control of the clock
timer
S1C62740 has a clock timer with OSC1 (crystal oscillation) as
basic oscillation built-in.
Clock timer data
The 128–1 Hz timer data of the clock timer can be read out with
TM0–TM7 registers (E3H and E4H).
Clock timer reset
By writing "1" on TMRST (E2H•D0), the clock timer is reset and all
timer data are set to "0".
Timer interrupt
The clock timer interrupt is generated at the falling edge of the
frequencies (32 Hz, 8 Hz, 2 Hz and 1 Hz). At this time, the corre-
sponding interrupt factor flag (IT32, IT8, IT2 and IT1) is set to "1".
Selection of whether to mask the separate interrupts can be made
with the interrupt mask registers (EIT32, EIT8, EIT2 and EIT1).
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
C6H
IT32
R
IT1
IT2
IT8
IT32
0
0
0
0
Interrupt factor flag (clock timer 1 Hz)
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
Yes
Yes
Yes
No
No
No
No
IT8IT2IT1
*4
*4
*4
*4
*7
CCH
EIT32
EIT1
EIT2
EIT8
EIT32
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
EIT8EIT2EIT1
R/W
Interrupt mask register (clock timer 1 Hz)
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
E2H
TMRST
W
0
0
0
TMRST
Reset
–
000
–
–
–
–
*2
*2
*2
*2
*5
*5
*5
*5
TM0
R
TM3
TM2
TM1
TM0
–
–
–
–
TM1TM2TM3
E3H
*3
*3
*3
*3
Unused
Unused
Unused
Clock timer and watchdog timer reset
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
R
TM4
R
TM7
TM6
TM5
TM4
–
–
–
–
TM5TM6TM7
E4H
*3
*3
*3
*3
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)