Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-29
CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports)
Loading P00–P03 output data into A register
Label Mnemonic/operand Comment
;*
;* I/O PORT
;*
;* LOADING P00-P03 OUTPUT DATA INTO A REGISTER
;
ZIOC EQU 0D6H ;I/O PORT CONTROL REGISTER
ZPUP EQU 0D7H ;I/O PORT PULL-UP CONTROL REGISTER
ZP0 EQU 0D8H ;I/O PORT P00-P03
;
LD Y,ZPUP ;SET PULL-UP CONTROL
;REGISTER ADDRESS
AND MY,1110B ;DISABLE P00-P03 PULL UP RESISTORS
LD Y,ZIOC ;SET I/O PORT CONTROL ADDRESS
OR MY,0001B ;SET P00-P03 AS OUTPUT PORT
LD Y,ZP0 ;SET ADDRESS OF P00-P03
LD A,MY ;LOAD DATA INTO A REGISTER
;
As shown in Figure 6.5.2, the fabove program loads the data of the
I/O ports into the A register.
P03 P02 P01 P00
Data register
P00
Data register
P01
Data register
P02
Data register
P03
A register
D3 D2 D1 D0
Fig. 6.5.2
Control of I/O port (Input)
Data can be loaded from the I/O port into the B register or MX
instead of the A register.