Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

II-28 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports)
How to set as output
Set "1" in the I/O port control register D6H, D0 (D1 for P1, D2 for
P2) and the I/O port (P00–P03) is set as an output port. The state
of the I/O port (P00–P03) is decided by the address D8H (D9H for
P1, DAH for P2). This data is held by the register, and can be set
regardless of the contents of the I/O control registers. (The data
can be set whether I/O ports are input ports or output ports is
read directly.)
If perform the read out I/O port in each mode;
when output mode,
the register value is read out, and when input mode, the port value
(input voltage level) is read out.
The I/O control registers are cleared to "0" (input/output ports are
set as input ports), and the data registers are also cleared to "0"
after an initial reset.
Note: P2 port can be used as general I/O port or serial interface port. It is
selected by PFS (DBH•D3). When PFS is set to "0", then P2 port is an I/O
port. When PFS is set to "1", then P2 port is a serial interface port.
Example program
for the I/O ports
Following program shows the I/O ports controlling procedure.
Loading P00–P03 input data into A register
Label Mnemonic/operand Comment
;*
;* I/O PORT
;*
;* LOADING P00-P03 INPUT DATA INTO A REGISTER
;
ZIOC EQU 0D6H ;I/O PORT CONTROL REGISTER
ZPUP EQU 0D7H ;I/O PORT PULL-UP CONTROL REGISTER
ZP0 EQU 0D8H ;I/O PORT P00-P03
;
LD Y,ZIOC ;SET I/O PORT CONTROL ADDRESS
AND MY,1110B ;SET P00-P03 AS INPUT PORT
LD Y,ZPUP
;SET PULL-UP CONTROL REGISTER ADDRESS
OR MY,0001B ;PULL UP P00-P03 TO VDD
LD Y,ZP0 ;SET ADDRESS OF P00-P03
LD A,MY ;LOAD DATA INTO A REGISTER
;
Fig. 6.5.1
Loading into the A register
D3
P03
D2
P02
D1
P01
D0
P00
A register
As shown in Figure 6.5.1, the above program loads the data of the
I/O ports into the A register.