Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-27
CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports)
I/O Ports (P00–P03, P10–P13 and P20–P23)6.5
I/O data memory of
the I/O ports
The control registers of the I/O ports are shown in Table 6.5.1.
Table 6.5.1 Control registers of I/O ports
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Control of the I/O
ports
The S1C62740 contains 3 sets of general I/O port (4 bits × 3).
These ports can be use as input port or output port, according to
I/O port control register IOC (D6H). When IOC is "0", the port is set
for input, when it is "1", the port is set for output.
How to set as input
Set "0" in the I/O port control register D6H, D0 (D1 for P1, D2 for
P2) and the I/O port (P00–P03) is set as an input port. The state of
the I/O port (P00–P03) is decided by the address D8H (D9H for P1,
DAH for P2). (In the input mode, the port level is read directly.)
The P0, P1 and P2 I/O ports can be pull up by software. Set "1" in
the I/O pull up control register D7H, D0 (D1 for P1, D2 for P2) and
the pull up register will directly connect to P00–P03 internally.
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
D6H
IOC0
R
0
IOC2
IOC1
IOC0
–
0
0
0
Output
Output
Output
Input
Input
Input
IOC1IOC20
*2
*6
D7H
PUP0
R/W
0
PUP2
PUP1
PUP0
–
0
0
0
Unused
Pull up control register 2 (P20–P23)
Pull up control register 1 (P10–P13)
Pull up control register 0 (P00–P03)
On
On
On
Off
Off
Off
PUP1PUP20
*2
*6
D8H
P00
P03
P02
P01
P00
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P01P02P03
*2
*2
*2
*2
D9H
P10
P13
P12
P11
P10
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P11P12P13
*2
*2
*2
*2
DAH
P20
P23
P22
P21
P20
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P21P22P23
*2
*2
*2
*2
R/W
*7
R/W
R/W
Unused
I/O control register 2 (P20–P23)
I/O control register 1 (P10–P13)
I/O control register 0 (P00–P03)
R/W
R
I/O port (P00–P03)
I/O port (P10–P13)
I/O port (P20–P23)
When P20–P23 is selected as SIO port, P20–
P23 registers will function as register only
*5
*5