Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL SOFTWARE EPSON II-23
CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports)
Following program shows the output ports controlling procedure in
ordinary DC output case.
Loading B register data into R00–R03
Label Mnemonic/operand Comment
Example program
for the general
output ports
;*
;* OUTPUT PORT
;*
;* LOADING DATA OF B REGISTER TO R00-R03
;
ZR0 EQU 0D4H ;R0 OUTPUT PORT
ZBZCTL EQU 0E0H ;BUZZER CONTROL REGISTER
BZR03 EQU 1000B ;R03 PORT OUTPUT SELECTION
BZR02 EQU 0100B ;R02 PORT OUTPUT SELECTION
ZFOCTL EQU 0E1H ;FOUT CONTROL REGISTER
FOR00 EQU 1000B ;R00 OUTPUT PORT SELECTION
ZPTC EQU 0E9H ;PROGRAMMABLE TIMER CONTROL REGISTER
PTR01 EQU 1000B ;R01 PORT OUTPUT SELECTION
;
LD X,ZBZCTL ;DISABLE BUZZER OUTPUT TO R03 & R02
AND MX,(NOT (BZR02 OR BZR03)) AND 0FH
LD X,ZFOCTL ;DISABLE FOUT OUTPUT TO R00
AND MX,(NOT FOR00) AND 0FH
LD X,ZPTC ;DISABLE PTOVF OUTPUT TO R01
AND MX,(NOT PTR01) AND 0FH
;
LD X,ZR0 ;SET OUTPUT PORT ADDRESS
LD MX,B ;OUTPUT B REGISTER TO R0 PORT
;
As shown in Figure 6.4.1, the above program loads the data of the
B register into the output ports.
D3 D2 D1 D0
Data register
R00
Data register
R01
Data register
R02
Data register
R03
B register
Fig. 6.4.1
Correspondence between output
ports (R00–R03) and B register
The output data can be taken from the A register, MX, or immedi-
ate data instead of B register.