Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

II-20 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports)
Following program shows the input ports controlling procedure.
Label Mnemonic/operand Comment
Example program
for the input ports
;*
;* INPUT PORT
;*
ZIK1 EQU 0C2H ;K10 INTERRUPT FACTOR FLAG
ZIK0 EQU 0C3H ;K0 INTERRUPT FACTOR FLAG
ZEIK EQU 0C9H ;K0, K10 INTERRUPT MASK REGISTER
EIK1 EQU 0010B ;K10
EIK0 EQU 0001B ;K0
ZSIK0 EQU 0CAH ;K0 INTERRUPT SELECTION REGISTER
ZK0 EQU 0D0H ;K0 INPUT PORT
ZK1 EQU 0D1H ;K10 INPUT PORT
ZDFK0 EQU 0D2H ;K0 DIFFERENTIAL REGISTER
ZDFK1 EQU 0D3H ;K10 DIFFERENTIAL REGISTER
;
ORG 108H
JP K0INT ;K0 INTERRUPT ROUTINE
ORG 10AH
JP K1INT ;K10 INTERRUPT ROUTINE
;
K0K10:
;* INPUT PORT K0 & K10 INITIAL ROUTINE
;
LD X,ZK0 ;INITIALIZE FOR
;DIFFERENTIAL REGISTERS
LD Y,ZDFK0
LD MY,MX
LD X,ZK1
LD Y,ZDFK1
LD MY,MX
;
DI
LD X,EIK
LD MX,EIK1 OR EIK0
;ENABLE K0 AND K1 INPUT PORT
LD X,ZSIK0 ;ENABLE K00, K01, K02, K03
LD MX, 0FH
LD X,ZIK1 ;RESET INTERRUPT FLAG
LDPX A,MX
LD A,MX
EI
RET
;
K0INT:
;* K0 INTERRUPT SERVICE ROUTINE
;
LD X,ZIK0
LD A,MX
;: