Specifications

S1C62740 TECHNICAL SOFTWARE EPSON II-19
CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports)
Interrupt mask register
EIK0
1
Interrupt selection register Input comparison register
SIK03 SIK02 SIK01 SIK00
DFK03 DFK02 DFK01 DFK00
1110 1010
With the above setting, the interrupt of K00–K03 is generated under the
following condition:
Input ports
(1) K03 K02 K01 K00
1010 (Initial value)
↓
(2) K03 K02 K01 K00
1011
↓
(3) K03 K02 K01 K00
0011 → Interrupt generation
↓
(4) K03 K02 K01 K00
0111
Because K00 is masked, interrupt will
be generated when no matching
occurs between the contents of the 3
bits K01–K03 and the 3 bits input
comparison registers DFK01–DFK03.
Fig. 6.3.1
Example of an interrupt
for K00–K03
Interrupt mask register Input comparison register
EIK1 DFK10
11
With the above setting, the interrupt of K10 is generated under the following
condition:
Input ports
(1) K10
1 (Initial value)
↓
(2) K10
0 → Interrupt generation
Because K10 is not matched with DFK10.
Fig. 6.3.2
Example of an interrupt for K10