Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-18 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports)
Reading of input data
Input data of the input port terminal may be read out with regis-
ters K00–K03 and K10. The terminal voltage of 5 bits input ports
are each reading as "1" and "0" at high (V
DD) level and low (VSS)
level, respectively.
Input interrupt (K00–K03)
The input interrupt timing of K00–K03 can be set to generate
interrupt at the rising edge or falling edge of the input by the
setting of input comparison registers DFK00–DFK03. When DFK
register is set to "1", the falling edge of the input becomes an
interrupt generating condition, the rising edge when set to "0".
Moreover, the interrupt mask can be set with the interrupt mask
register EIK0. And each K00–K03 inputs interrupt can be selected
by the interrupt selection registers SIK00–SIK03. So if you want
enable interrupt, for example K03, set EIK0 and SIK03 to "1".
However, if the interrupt of any one of K00–K03 is enabled, inter-
rupt will be generated when the content change from matched to
no matched with the input comparison register.
When interrupt is generated, the interrupt factor flag IK0 is set to
"1".
Figure 6.3.1 shows an example of an interrupt for K00–K03.
Input interrupt (K10)
The input interrupt timing of K10 can be set to generate interrupt
at the rising edge or falling edge of the input by the setting of input
comparison registers DFK10. When DFK10 register is set to "1", the
falling edge of the input becomes an interrupt generating condition,
the rising edge when set to "0".
The interrupt mask can be selected with the interrupt mask regis-
ter EIK1. When interrupt is generated, the interrupt factor flag IK1
is set to "1".
Figure 6.3.2 shows an example of an interrupt for K10.
Control of the input
ports