Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL SOFTWARE EPSON II-17
CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports)
Input Ports (K00–K03 and K10)6.3
I/O data memory of
the input ports
The control registers of the input ports are shown in Table 6.3.1.
Table 6.3.1 Control registers of input ports
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
C2H
IK1
R
0
0
0
IK1
Yes No
000
–
–
–
0
*2
*2
*2
*5
*5
*5
*4
IK0
R
0
0
0
IK0
–
–
–
0
Yes No
000
C3H
*2
*2
*2
*5
*5
*5
*4
C9H
EIK0
0
0
EIK1
EIK0
–
–
0
0
Unused
Unused
Interrupt mask register (K10)
Interrupt mask register (K00–K03)
Enable
Enable
Mask
Mask
EIK100
*2
*2
*5
*5
*7
R/W
Unused
Unused
Unused
Interrupt factor flag (K10)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
R
D0H
K00
R
K03
K02
K01
K00
–
–
–
–
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
K01K02K03
*2
*2
*2
*2
D1H
K10
R
0
0
0
K10
–
–
–
–
High Low
000
*2
*2
*2
*2
*5
*5
*5
D2H
DFK00
R/W
DFK03
DFK02
DFK01
DFK00
DFK01DFK02DFK03
1
1
1
1
DFK10
R
0
0
0
DFK10
–
–
–
1
000
D3H
*2
*2
*2
*5
*5
*5
Unused
Unused
Unused
Input port (K10)
Unused
Unused
Unused
Input comparison register (K10)
Input comparison register (K00–K03)
R/W
CAH
SIK00
SIK03
SIK02
SIK01
SIK00
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
SIK01SIK02SIK03
R/W
Interrupt selection register (K03)
Interrupt selection register (K02)
Interrupt selection register (K01)
Interrupt selection register (K00)