Specifications

S1C62740 TECHNICAL SOFTWARE EPSON II-15
CHAPTER 6: PERIPHERAL CIRCUITS (OSC3)
OSC3
S1C62740 has two built-in oscillation circuits (OSC1 and OSC3).
6.2
I/O data memory of
the OSC3
The control registers of the OSC3 are shown in Table 6.2.1.
Table 6.2.1 Control registers of OSC3
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Control of the OSC3
When processing of the S1C62740 requires high-speed operations,
the CPU's operating clock should be switched from OSC1 to OSC3.
When the S1C62740's CPU clock is to be OSC3, first set OSCC to
"1" (OSC3 oscillation goes on), and then, after about 5 msec, set
CLKCHG to "1" (switching from OSC1 to OSC3).
When switching the clock from OSC3 to OSC1, first set CLKCHG to
"0", and then set OSCC to "0". In this case, use a separate instruc-
tion for switching the clock and OSC3 OFF.
Example program
for the OSC3
Following program shows the oscillation clock controlling proce-
dure.
Label Mnemonic/operand Comment
;*
;* OSC3 CLOCK CONTROL
;*
ZOSCC EQU 0DFH ;CPU CLOCK CONTROL
CLKCHG EQU 0010B ;CPU SYSTEM CLOCK SWITCH
OSCC EQU 0001B ;OSC3 OSCILLATION ON/OFF
;
OS3:
;* CHANGE CLOCK FREQUENCY FROM OSC1 TO OSC3
LD X,ZOSCC ;SET OSC3 TO ON
OR MX,OSCC
;
LD A,0EH ;WAIT 5mS
OS3DLP:
ADD A,0FH
JP NZ,OS3DLP
;
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
*7
DFH
OSCC
0
0
CLKCHG
OSCC
–
–
0
0
OSC3
On
OSC1
Off
CLKCHG00
*5
*5
R/W
Unused
Unused
CPU system clock switch
OSC3 oscillation On/Off
*2
*2
R