Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL SOFTWARE EPSON II-11
CHAPTER 5: INITIAL RESET
5.2 Example Program for the System
Initialization
Following program shows the example of the procedure for system
initialization.
Label Mnemonic/operand Comment
;*
;* INITIAL RESET PROGRAM
;*
;
ORG 100H
;
JP INIT
;
ORG 110H
;
INIT:
;* INITIALIZE CPU CORE AT THE BEGINNING
;
RST F,0000B ;CLEAR IDZC FLAGS
;
LD A,08H ;SET STACK POINTER TO 080H
LD SPH,A
LD A,00H
LD SPL,A
;
;* CLEAR DATA MEMORY
;
CLR: LD A,0 ;CLEAR PAGE 0 AND 1
LD XP,A
LD A,1
LD YP,A
LD X,00H
LD Y,00H
CLR1: LBPX MX,0H ;CLEAR RAMS
LDPY MY,0H
LDPY MY,0H
CP XH,08H ;CONTINUE TILL 080H
JP C,CLR1
;
LD A,2 ;CLEAR PAGE 2 AND 3
LD XP,A
LD A,3
LD YP,A
LD X,00H
LD Y,00H
CLR2: LBPX MX,0H ;CLEAR RAMS