Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-8 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 4: DATA MEMORY
Table 4.2.1(c) I/O memory map (E0H–EFH)
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
E0H
BZFQ
R/W
BZR03
BZR02
0
BZFQ
0
0
–
0
R03 port output selection
R02 port output selection
Unused
Buzzer frequency selection
Buzzer
Buzzer
2kHz
DC
DC
4kHz
0BZR02BZR03
*2
*5
E1H
FOFQ0
R/W
FOR00
0
FOFQ1
FOFQ0
0
–
0
0
FOUT DC
FOFQ10FOR00
*2
*5
E2H
TMRST
W
0
0
0
TMRST
Reset
–
000
–
–
–
–
*2
*2
*2
*2
*5
*5
*5
*5
TM0
R
TM3
TM2
TM1
TM0
–
–
–
–
TM1TM2TM3
E3H
*3
*3
*3
*3
E6H
SWRST
R
0
0
SWRUN
SWRST
–
–
0
Reset
Run
Reset
Stop
–
SWRUN
00
*2
*2
*5
*5
*5
E7H
SWL0
SWL3
SWL2
SWL1
SWL0
0
0
0
0
SWL1SWL2SWL3
E8H
SWH0
SWH3
SWH2
SWH1
SWH0
0
0
0
0
SWH1SWH2SWH3
E9H
PTRST
W
PTR01
0
PTRUN
PTRST
0
–
0
–
R01 port output selection
Unused
Programmable timer Run/Stop
Programmable timer reset (reload)
PTOVF
Run
Reset
DC
Stop
–
PTRUN
R/W
0
R
PTR01
R/W
*2
*2
*5
*5
EAH
PTC0
PTD1
PTD0
PTC1
PTC0
0
0
0
0
PTC1PTD0PTD1
R/W
*7
EBH
PT0
R
PT3
PT2
PT1
PT0
–
–
–
–
PT1PT3
*3
*3
*3
*3
ECH
PT4
PT7
PT6
PT5
PT4
–
–
–
–
PT5PT6PT7
*3
*3
*3
*3
R
Programmable timer pre-divider selection
0: 1/256, 1: 1/32, 2: 1/4, 3: 1/1
Programmable timer clock source selection
0: K10 (NR), 1: K10, 2: fOSC1, 3: fOSC3
R
R00 port output selection
Unused
FOUT frequency selection
0: 512 Hz, 1: 4096 Hz, 2: fOSC1, 3: fOSC3
Unused
Unused
Unused
Clock timer and watchdog timer reset
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Unused
Unused
Stopwatch timer Run/Stop
Stopwatch timer reset
PT2
EDH
RD0
RD3
RD2
RD1
RD0
–
–
–
–
RD1RD2RD3
R/W
EEH
RD4
RD7
RD6
RD5
RD4
–
–
–
–
RD5RD6RD7
R/W
EFH
LCDON
R/W
LDTY1
LDTY0
0
LCDON
0
0
–
0
On Off
0
R
LDTY0LDTY1
*5
LCD drive duty selection
0: 1/4, 1: 1/3, 2: 1/2, 3: 1/1
Unused
LCD display control (LCD display all off)
R/W
R
Stopwatch timer data 1/10 sec (BCD)
MSB
LSB
*3
*3
*3
*3
*3
*3
*3
*3
*2
Programmable timer reload data
(low-order 4 bits)
LSB
Programmable timer reload data
(high-order 4 bits)
MSB
R/W
WD0
WDRST
0
WD1
WD0
Reset
–
0
0
Reset
–
WD10WDRST
E5H
*2
*5
*5
Watchdog timer reset
Unused
Watchdog timer data (1/4 Hz)
Watchdog timer data (1/2 Hz)
RR/W
RR/W
R
TM4
R
TM7
TM6
TM5
TM4
–
–
–
–
TM5TM6TM7
E4H
*3
*3
*3
*3
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
WR
W
Stopwatch timer data 1/100 sec (BCD)
MSB
LSB
Programmable timer data (low-order 4 bits)
LSB
Programmable timer data (high-order 4 bits)
MSB