Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL SOFTWARE EPSON II-7
CHAPTER 4: DATA MEMORY
Table 4.2.1(b) I/O memory map (D0H–DFH)
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
D0H
K00
R
K03
K02
K01
K00
–
–
–
–
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
K01K02K03
*2
*2
*2
*2
D1H
K10
R
0
0
0
K10
–
–
–
–
High Low
000
*2
*2
*2
*2
*5
*5
*5
D2H
DFK00
R/W
DFK03
DFK02
DFK01
DFK00
DFK01DFK02DFK03
1
1
1
1
DFK10
R
0
0
0
DFK10
–
–
–
1
000
D3H
*2
*2
*2
*5
*5
*5
D4H
R00
FOUT
R/W
R03
BZ
R02
BZ
R01
PTOVF
R00
FOUT
0
0
1
1
High
On
High
On
High
Off
High
Off
Low
Off
Low
Off
Low
On
Low
On
R01
PTOVF
R02
BZ
R03
BZ
D6H
IOC0
R
0
IOC2
IOC1
IOC0
–
0
0
0
Output
Output
Output
Input
Input
Input
IOC1IOC20
*2
*5
D7H
PUP0
R/W
0
PUP2
PUP1
PUP0
–
0
0
0
Unused
Pull up control register 2 (P20–P23)
Pull up control register 1 (P10–P13)
Pull up control register 0 (P00–P03)
On
On
On
Off
Off
Off
PUP1PUP20
*2
*5
D8H
P00
P03
P02
P01
P00
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P01P02P03
*2
*2
*2
*2
D9H
P10
P13
P12
P11
P10
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P11P12P13
*2
*2
*2
*2
DAH
P20
P23
P22
P21
P20
–
–
–
–
High
High
High
High
Low
Low
Low
Low
P21P22P23
*2
*2
*2
*2
R/W
*7
DBH
SCS0
R/W
PFS
SDP
SCS1
SCS0
0
0
0
0
Serial I/F
LSB first
I/O port
MSB first
SCS1PFS
*6
DCH
SCTRG
0
0
SCRUN
SCTRG
–
–
0
–
Run
Trigger
Stop
–
SCRUN00
*2
*2
*2
*5
*5
*5
R/W
R/W
P2 port function selection
Serial data input/output permutation
R
Unused
Unused
Serial interface status
Serial interface clock trigger
Unused
Unused
Unused
Input port (K10)
Unused
Unused
Unused
Input comparison register (K10)
Output port (R03)
Buzzer inverted output
Output port (R02)
Buzzer output
Output port (R01)
PTOVF output
Output port (R00)
FOUT output
Unused
I/O control register 2 (P20–P23)
I/O control register 1 (P10–P13)
I/O control register 0 (P00–P03)
SDP
DDH
SD0
SD3
SD2
SD1
SD0
–
–
–
–
SD1SD2SD3
R/W
DEH
SD4
SD7
SD6
SD5
SD4
–
–
–
–
SD5SD6SD7
R/W
DFH
OSCC
0
0
CLKCHG
OSCC
–
–
0
0
OSC3
On
OSC1
Off
CLKCHG00
*5
*5
R/W
Unused
Unused
CPU system clock switch
OSC3 oscillation On/Off
Input comparison register (K00–K03)
R/W
R/W
R
I/O port (P00–P03)
I/O port (P10–P13)
I/O port (P20–P23)
When P20–P23 is selected as SIO port, P20–
P23 registers will function as register only.
Serial interface clock mode selection
0: slave, 1: PTOVF, 2: CLK/2, 3: CLK
W
*2
*2
*2
*2
*2
*2
*2
*2
*2
*2
Serial interface data (low-order 4 bits)
LSB
Serial interface data (high-order 4 bits)
MSB
R
*6
*6