Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL SOFTWARE EPSON II-3
CHAPTER 3: PROGRAM MEMORY (ROM)
PROGRAM MEMORY (ROM)CHAPTER 3
3.1 Configuration of the ROM
S1C62740 is built-in with 4,096 steps × 12 bits mask ROM for
program storage.
The program area is 16 (0–15) pages, each 256 (00H–FFH) steps.
After initial reset, the program beginning address is page 1, step
00H. The interrupt vector is allocated to page 1, steps 02H–0FH.
The configuration of the ROM is as shown in Figure 3.1.1.
Fig. 3.1.1
Configuration of the ROM
3.2 Interrupt Vector
The interrupt vector and interrupt request correspondence is
shown in Table 3.2.1.
Table 3.2.1
Interrupt request and interrupt
vector
Interrupt vector
(PCP and PCS)
102H Clock timer interrupt Low
104H Stopwatch timer interrupt ↑
106H A/D converter interrupt
108H Input (K00–K03) interrupt
10AH Input (K10) interrupt
10CH Serial interface interrupt ↓
10EH Programmable timer interrupt High
* Sleep cancelled by: 1. Input (K10) interrupt
2. System reset
When multiple interrupts simultaneously occur, the high priority
vector address is set to the program counter.
Interrupt request Priority
Program start address
Interrupt vector address
0 page
00H step
01H step
02H step
0FH step
10H step
FFH step
12 bits
1 page
2 page
3 page
4 page
5 page
6 page
7 page
8 page
9 page
10 page
11 page
12 page
13 page
14 page
15 page
Program area