Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
II-2 EPSON S1C62740 TECHNICAL SOFTWARE
CHAPTER 2: BLOCK DIAGRAM
BLOCK DIAGRAM
The S1C62740 block diagram is shown in Figure 2.1.
CHAPTER 2
LOGIC
POWER
CONTROL
and SVD
INTERRUPT
CONTROL
PROG.
TIMER or
EVENT
COUNTER
K00–K03
K10
RAM
512 x 4
COM0–
COM3
SEG0–
SEG31
DD
CA
C1
C2
C3
D1
SS
P00–P03
P10–P13
P20–P23
SYSTEM
RESET
CONTROL
ROM
4,096 x 12
CORE CPU S1C6200A
OSC
and
SLEEP
LCD
DRIVER
32 x 4
OSC1
OSC2
OSC3
OSC4
ANALOG
POWER
CONTROL
DDA
RA
R1
R2
SSA
A/D
CONVERTER
AI0
AI1
AI2
AI3
AI4
AIF
BF
RI
CI
CAZ
CO
OP-AMP
AIP0, 1
AIM0, 1
AOUT0, 1
TIMER
STOP
WATCH
OUTPUT
PORT
INPUT
PORT
I/O
PORT
FOUT &
BUZZER
SERIAL
I/O PORT
RESET
TEST
R00–R03
S1C62740 BLOCK DIAGRAM
V
V
V
V
V
CA
CB
CC
V
V
V
V
V
V
CH
CL
GND
V
Fig. 2.1
S1C62740 block
diagram