Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-118 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 5: SUMMARY OF NOTES
However, when fOSC1 is selected for CPU system clock, the
instruction cycles are long enough, so there is no need to worry
about maintaining 100 µsec for SVDON = "1" in the software.
(2) The SVD circuit should normally be turned OFF as the con-
sumption current of the IC becomes large when it is ON.
Interrupt and HALT/
SLEEP
(1) When it shifts to the SLEEP status, you must invariably set the
K10 interrupt to enable.
(2) When shifting to the SLEEP status, the CPU clock must be set
to OSC1 and the OSC3 oscillation circuit must be off.
(3) The interrupt factor flags are set when the timing condition is
established, even if the interrupt mask registers are set to "0".
(4) Write the interrupt mask register only in the DI status (inter-
rupt flag = "0"). Writing during EI status (interrupt flag = "1")
will cause malfunction.
(5) Reading of interrupt factor flags is available at EI, but be careful
in the following cases.
If the interrupt mask register value corresponding to the inter-
rupt factor flags to be read is set to "1", an interrupt request will
be generated by the interrupt factor flags set timing, or an
interrupt request will not be generated. Be very careful when
interrupt factor flags are in the same address.