Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-112 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
Table 4.15.4(b) Control bits of interrupt (2)
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Interrupt mask registers (CCH)
Interrupt factor flags (C6H)
See Section 4.8, "Clock Timer".
EIT32, EIT8, EIT2, EIT1:
IT32, IT8, IT2, IT1:
EISW0, EISW1:
ISW0, ISW1:
Interrupt mask registers (CBH•D0, D1)
Interrupt factor flags (C5H•D0, D1)
See Section 4.9, "Stopwatch Timer".
EIAD:
IAD:
Interrupt mask register (C8H•D2)
Interrupt factor flag (C4H•D0)
See Section 4.12, "A/D Converter".
DFK00–DFK03:
SIK00–SIK03:
EIK0:
IK0:
Input comparison registers (D2H)
Interrupt selection registers (CAH)
Interrupt mask register (C9H•D0)
Interrupt factor flag (C3H•D0)
See Section 4.4, "Input Ports".
DFK10:
EIK1:
IK1:
Input comparison register (D3H•D0)
Interrupt mask register (C9H•D0)
Interrupt factor flag (C3H•D0)
See Section 4.4, "Input Ports".
EISIO:
ISIO:
Interrupt mask register (C8H•D1)
Interrupt factor flag (C1H•D0)
See Section 4.11, "Serial Interface".
EIPT:
IPT:
Interrupt mask register (C8H•D0)
Interrupt factor flag (C0H•D0)
See Section 4.10, "Programmable Timer".
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
*7
CCH
EIT32
EIT1
EIT2
EIT8
EIT32
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
EIT8EIT2EIT1
R/W
Interrupt mask register (clock timer 1 Hz)
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
D2H
DFK00
R/W
DFK03
DFK02
DFK01
DFK00
DFK01DFK02DFK03
1
1
1
1
DFK10
R
0
0
0
DFK10
–
–
–
1
000
D3H
*2
*2
*2
*5
*5
*5
Unused
Unused
Unused
Input comparison register (K10)
Input comparison register (K00–K03)
R/W