Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-109
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
The interrupt factor flags can be masked by the corresponding
interrupt mask registers.
The interrupt mask registers are read/write registers. They are
enabled (interrupt authorized) when "1" is written to them, and
masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.15.2 shows the correspondence between interrupt mask
registers and interrupt factor flags.
Interrupt mask
Table 4.15.2
Interrupt mask registers and
interrupt factor flags
Note: Write the interrupt mask register only in the DI status (interrupt flag = "0").
Writing during EI status (interrupt flag = "1") will cause malfunction.
Interrupt mask register Interrupt factor flag
EIT1 (CCH•D3) IT1 (C6H•D3)
EIT2 (CCH•D2) IT2 (C6H•D2)
EIT8 (CCH•D1) IT8 (C6H•D1)
EIT32 (CCH•D0) IT32 (C6H•D0)
EISW1 (CBH•D1) ISW1 (C5H•D1)
EISW0 (CBH•D0) ISW0 (C5H•D0)
EIAD (C8H•D2) IAD (C4H•D0)
EIK0 (C9H•D0) IK0 (C3H•D0)
EIK1 (C9H•D1) IK1 (C2H•D0)
EISIO (C8H•D1) ISIO (C1H•D0)
EIPT (C8H•D0) IPT (C0H•D0)