Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-108 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
Table 4.15.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding
interrupt factors.
The CPU operation is interrupted when any of the conditions below
set an interrupt factor flag to "1".
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be reset to
"0" when the register data is read out.
At initial reset, the interrupt factor flags are reset to "0".
Interrupt factor
Table 4.15.1
Interrupt factors
Interrupt factor Interrupt factor flag
Clock timer 1 Hz falling edge IT1 (C6H•D3)
Clock timer 2 Hz falling edge IT2 (C6H•D2)
Clock timer 8 Hz falling edge IT8 (C6H•D1)
Clock timer 32 Hz falling edge IT32 (C6H•D0)
Stopwatch timer 1 Hz falling edge ISW1 (C5H•D1)
Stopwatch timer 10 Hz falling edge ISW0 (C5H•D0)
A/D converter
reverse integration has completed IAD (C4H•D0)
Input data (K00–K03)
rising or falling edge IK0 (C3H•D0)
Input data (K10)
rising or falling edge IK1 (C2H•D0)
Serial interface
data (8 bits) input/output has completed ISIO (C1H•D0)
Programmable timer
counter = 0 IPT (C0H•D0)
Note: Reading of interrupt factor flags is available at EI, but be careful in the
following cases.
If the interrupt mask register value corresponding to the interrupt factor
flags to be read is set to "1", an interrupt request will be generated by the
interrupt factor flags set timing, or an interrupt request will not be gener-
ated. Be very careful when interrupt factor flags are in the same address.