Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-105
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
SVDDT:
SVD data
(FFH•D1)
This is the result of supply voltage detection.
When "0" is read: Supply voltage (V
DDA–VSSA) ≥ Criteria voltage
When "1" is read: Supply voltage (V
DDA–VSSA) < Criteria voltage
Writing: Invalid
The result of supply voltage detection at time of SVDON is set to "0"
can be read from this register.
At initial reset, SVDDT is set to "0".
Programming notes
(1) To obtain a stable SVD detection result, the SVD circuit must
be on for at least l00 µsec. So, to obtain the SVD detection
result, follow the programming sequence below.
➀ Set SVDON to "1"
➁ Maintain for 100 µsec minimum
➂ Set SVDON to "0"
➃ Read SVDDT
However, when f
OSC1 is selected for CPU system clock, the
instruction cycles are long enough, so there is no need to worry
about maintaining 100 µsec for SVDON = "1" in the software.
(2) The SVD circuit should normally be turned OFF as the con-
sumption current of the IC becomes large when it is ON.