Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-99
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
AD0–AD12:
A/D conversion data
(F7H, F8H, F9H, FAH•D0)
The A/D conversion result counted by the dual slope counter is
binary data.
This data is effective from the time when the reverse integration
period has terminated (when an interrupt has been generated)
until the next reverse integration period has been terminated and
during this time it reads in the order of the address
F7H→F8H→F9H→FAH.
At initial reset, these data is set to "0".
ADP:
Input voltage polarity
(FAH•D1)
Indicates the polarity of the analog input voltage.
When "1" is read: Positive (+)
When "0" is read: Negative (-)
Writing: Invalid
When the A/D converted analog input voltage is positive (+), the
ADP becomes "1" and when it is negative (-), it becomes "0".
At initial reset, the ADP is set to "0".
IDR:
Read data status
(FBH•D0)
Indicates whether the data that has been read is effective or
invalid.
When "1" is read: Data invalid
When "0" is read: Data effective
Writing: Invalid
It can decide whether the data that has been read is effective or
invalid by reading the IDR after data has been read.
When the reading of the data has completed before the next A/D
conversion terminates, the IDR is set to "1" to indicate data invalid,
so that the data will be rewritten. An IDR that has been set to "1" is
reset to "0" by reading.
At initial reset, the IDR is set to "0".
EIAD:
Interrupt mask register
(C8H•D2)
Select whether to mask interrupt with the A/D converter.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
The A/D interrupt is permitted when "1" is written in the EIAD.
When "0" is written, interrupt is masked.
At initial reset, this register is set to "0".