Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-96 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Table 4.12.4 shows the A/D converter control bit and its address.
Control of the A/D
converter
Table 4.12.4 Control bits of A/D converter
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
C4H
IAD
R
0
0
0
IAD
–
–
–
0
Yes No
000
*2
*2
*2
*5
*5
*5
*4
C8H
EIPT
0
EIAD
EISIO
EIPT
0
0
0
Unused
Interrupt mask register (A/D converter)
Interrupt mask register (serial interface)
Interrupt mask register (programmable timer)
Enable
Enable
Enable
Mask
Mask
Mask
EISIOEIAD0
*2
*5
*7
R/W
Unused
Unused
Unused
Interrupt factor flag (A/D converter)
R
F0H
VRON
R/W
GNDON1
GNDON0
VRAON
VRON
0
0
0
0
GND circuit On/Off and mode selection
0: Off, 1: On1, 2: On2, 3: On3
VR output voltage adjustment On/Off
VR circuit On/Off
On
On
Off
Off
VRAONGNDON0GNDON1
ADRS0
R
0
0
ADRS1
ADRS0
–
–
0
0
ADRS100
F3H
*2
*2
*5
*5
F6H
AI4
R
ADON
0
0
AI4
0
–
–
0
On
On
Off
Off
0
0ADON
*2
*2
*5
*5
F7H
AD0
AD3
AD2
AD1
AD0
0
0
0
0
AD1AD2AD3
F8H
AD4
AD7
AD6
AD5
AD4
0
0
0
0
AD5AD6AD7
F9H
AD8
AD11
AD10
AD9
AD8
0
0
0
0
AD9AD10AD11
*5
*5
FAH
AD12
0
0
ADP
AD12
–
–
0
0
(+) (-)
ADP00
*2
*2
R
FBH
IDR
R
0
0
0
IDR
–
–
–
0
Invalid Valid
00
*2
*2
*2
*5
*5
*5
R
R
Unused
Unused
Input voltage polarity
A/D converter count data (MSB)
Unused
Unused
Unused
Reading data status
Unused
Unused
A/D converter resolution selection
0: 6400, 1: 3200, 2: 1600, 3: 800
A/D converter clear and On/Off
Unused
Unused
Analog input terminal AI4 On/Off
0
R/W
R
A/D converter count data
AI0
AI3
AI2
AI1
AI0
0
0
0
0
On
On
On
On
Off
Off
Off
Off
AI1AI2AI3
F5H
Analog input terminal AI3 On/Off
Analog input terminal AI2 On/Off
Analog input terminal AI1 On/Off
Analog input terminal AI0 On/Off
AIS0
R/W
AIS3
AIS2
AIS1
AIS0
0
0
0
0
Resistor
Resistor
Differ. V
Differ. V
V(to GND)
V(to GND)
V(to GND)
V(to GND)
AIS1AIS2AIS3
F4H
AI4/AI3 mode selection
AI4/AI2 mode selection
AI3/AI2 mode selection
AI1/AI0 mode selection
R/W
R/W
A/D converter count data
LSB
R/W
A/D converter count data
*6