Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-90 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Since the slope of the reverse integral waveform is fixed, the coun-
ter value according to the integral result of the input voltage in step
(2) is obtained from the dual slope counter. The counter value n at
this time is indicated by the following expression.
0 = Vint - (-VR * n * T / CI * RI)
(Expression 4.12.2)
According to Expression 4.12.1 and Expression 4.12.2, it becomes
n = V
IN * N / VR (Expression 4.12.3)
The value of the input voltage is determined by reading and
processing this value using software.
V
IN = n * VR / N (Expression 4.12.4)
The reference voltage reverse integration period shown in Table
4.12.3 is the time for counting the full scale and, actually, the A/D
conversions is completed at the point where the output of the
integral AMP has become "0".
(4) Circuit related differences due to measurement items
The A/D conversion sequence does not differ depending on the
items selected. It responds to the respective selected items by
partially changing over the circuit.
• Voltage measurement mode
For voltage measurement, the GND level is added to the non-
inverted input of the integral AMP and the specified analog input is
A/D converted as opposite the GND level.
V
R2
is used for the reference voltage VR. (Calculate as VR = 163.8 mV.)
• Differential voltage measurement mode
For differential voltage measurement, the input level of AI0 (for
AI1–AI0 measurement) or the input level of AI2 (for AI3–AI2 meas-
urement) is added to the non-inverted input of the integral AMP
and the specified analog input of AI1 or AI3 is respectively A/D
converted as the opposite AI0 or opposite AI2 level.
V
R2
is used for the reference voltage VR. (Calculate as VR = 163.8 mV.)
Fig. 4.12.14
Circuit diagram at the
time of differential
voltage measurement
+
–
BUF
-VR
VR
V
IN
GND
+
–
+
–
CAZ CIBF
INT
CMP
S
1
RI
S
2
S
3
CO
AI0(AI2)
AI1(AI3)
VR = -V
R2
To A/D converter
control circuit