Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

S1C62740 TECHNICAL HARDWARE EPSON I-89
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
The slope of this integral output waveform changes in proportion to
the input voltage. The portion charged into the CAZ due to the
previous auto zero adjustment is added to the input voltage of the
integral AMP and negates the offset voltage. The input integration
period becomes the time that has been counted for only 1/2 the
number resolution counts that have specified the 32 kHz clock.
The integral AMP output voltage Vint at the point where this time
has elapsed is indicated by the following expression.
Vint = -V
IN * (N * T / CI * RI) (Expression 4.12.1)
VIN: Input voltage
N: 1/2 of the resolution (count number) specified by the software
Resolution N
6,552 3,276
3,276 1,638
1,638 819
820 410
T: OSC1 clock cycle 1/32,768 (sec)
CI: Integrating capacity
RI: Integrating resistance
(3) Reference voltage reverse integration period
When the input integration period is completed, the reference
voltage causes it to shift to the reverse integration period. The
switch S1 is connected to the VR or -VR side and switches S2 and
S3 go OFF.
The side of opposite polarity to the input voltage that effected the
integration in step (2) is selected for the polarity of the reference
voltage VR.
• When the input voltage VIN is positive: Switch S1 connects to the -VR side
• When the input voltage V
IN is negative: Switch S1 connects to the VR side
For this purpose, the polarity of the input voltage is checked by a
comparator for the input integration period, and which of the
polarities to be used is selected in advance.
At the same time as it begins the reverse integration by the refer-
ence voltage, the dual slope counter begins the count-up by the 32
kHz clock. The content of this counter is reset to the input integra-
tion period and hence counts up from "0".
Reverse integration continues until the comparator detects that the
output of the integral AMP has become "0" and at that point the
dual slope counter stops, then shifts to the next A/D conversion
sequence (auto zero adjustment period).