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Table Of Contents

MF654

Technical Manual

CMOS 4

BIT SINGLE CHIP MICROCOMPUTER

S1C62740 Technical Hardware/S1C62740 Technical Software

S1C62740

Summary of content (249 pages)

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MF654-05 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C62740 Technical Manual S1C62740 Technical Hardware/S1C62740 Technical Software
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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PREFACE This part explains the function of the S1C62740, the circuit configurations, and details the controlling method. II. S1C62740 Technical Software This part explains the programming method of the S1C62740. Software I. S1C62740 Technical Hardware Hardware This manual is individualy described about the hardware and the software of the S1C62740.
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The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
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Hardware I.
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CONTENTS CONTENTS CHAPTER 2 OVERVIEW ....................................................................... I-1 1.1 Features .................................................................................... I-2 1.2 Block Diagram ........................................................................... I-3 1.3 Pin Layout Diagram ................................................................... I-4 1.4 Pin Description ..........................................................................
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CONTENTS 4.4 Input Ports (K00–K03, K10) ..................................................... I-26 Configuration of input ports ................................................ I-26 Interrupt function ............................................................... I-27 Mask option ........................................................................ I-29 Control of input ports .......................................................... I-30 Programming notes .............................................
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CONTENTS Data input/output and interrupt function ........................... I-72 Mask option ........................................................................ I-74 Control of serial interface .................................................... I-75 Programming notes ............................................................. I-79 Configuration of A/D converter ........................................... I-80 Measured input terminal and measurement items ...............
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CONTENTS CHAPTER 8 CHAPTER 9 I-iv PACKAGE ..................................................................... I-130 8.1 Plastic Package ....................................................................... I-130 8.2 Ceramic Package for Test Samples ........................................ I-132 PAD LAYOUT ................................................................. I-133 9.1 Diagram of Pad Layout ........................................................... I-133 9.2 Pad Coordinates ......
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CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C62740 is a single-chip microcomputer made up of the 4-bit core CPU S1C6200A, ROM (4,096 words, 12 bits to a word), RAM (512 words, 4 bits to a word) LCD driver, dual slope type A/D converter, general purpose operational amplifier, serial interface, watchdog timer, programmable timer and time base counter.
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CHAPTER 1: OVERVIEW 1.1 Features OSC1 oscillation circuit .... OSC3 oscillation circuit .... Instruction set .... Instruction execution time .... (differ depending on instruction) ROM capacity .... RAM capacity .... Input port .... Output port .... I/O port .... Serial interface .... A/D converter .... Crystal oscillation circuit: 32,768 Hz (Typ.) CR or ceramic oscillation circuit (*1): 1 MHz (Typ.
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CHAPTER 1: OVERVIEW 1.2 Block Diagram S1C62740 BLOCK DIAGRAM OSC1 OSC2 OSC3 OSC4 CORE CPU S1C6200A ROM 4,096 x 12 OSC and SLEEP SYSTEM RESET CONTROL RAM 512 x 4 COM0– COM3 SEG0– SEG31 V DD V CA V C1 V C2 V C3 CA CB CC V D1 V SS AIP0, 1 AIM0, 1 AOUT0, 1 V DDA V RA V R1 V R2 CH CL GND V SSA Fig. 1.2.1 Block diagram AI0 AI1 AI2 AI3 AI4 AIF BF RI CI CAZ CO S1C62740 TECHNICAL HARDWARE RESET TEST INTERRUPT CONTROL LCD DRIVER 32 x 4 TIMER STOP WATCH LOGIC POWER CONTROL and SVD PROG.
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CHAPTER 1: OVERVIEW 1.3 Pin Layout Diagram QFP5-100pin 80 51 81 50 Index 100 31 1 30 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Fig. 1.3.1 Pin layout diagram (QFP5-100pin) I-4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K02 K01 K00 N.C. N.C.
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CHAPTER 1: OVERVIEW QFP15-100pin 75 51 76 50 Index 100 26 1 25 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Fig. 1.3.2 Pin layout diagram (QFP15-100pin) S1C62740 TECHNICAL HARDWARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K00 N.C. N.C.
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CHAPTER 1: OVERVIEW 1.4 Pin Description Pin name VDD VSS VDDA VSSA GND VD1 VC1 VC2 VC3 VCA CA–CC OSC1 OSC2 OSC3 OSC4 K00–10 P00–13 P20–23 R00–03 COM0–3 SEG0–31 AI0–4 AIF CAZ CI RI BF CO CH CL VR1 VR2 VRA AIP0 AIM0 AOUT0 AIP1 AIM1 AOUT1 RESET TEST I-6 Table 1.4.1 Pin description Pin No.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (3 V *1) supplied to VDD/VDDA through VSS/VSSA, the S1C62740 generates the necessary internal voltage with the regulated voltage circuit ( for oscillators, for LCDs), the voltage booster circuit ( for LCDs) and the voltage dividing circuit ( ≈ VDDA/2, reference voltage for analog circuit). Figure 2.1.1 shows the configuration of power supply.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET Voltage for oscillation circuit and internal circuit VD1 is the voltage of the oscillation circuit and the internal logic circuit, and is generated by the oscillation system regulated voltage circuit for stabilizing the oscillation. Making VSS the standard (logic level 0), the oscillation system regulated voltage circuit generates VD1 from the supply voltage that is input from the VDD–VSS terminals.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET The GND (ground) explained here following becomes the standard for both VR1 and VR2 and becomes the electric potential of the VSS side. Refer to the section "A/D Converter" for details such as circuit configuration. Note: Since the built-in reference voltage generation circuit is under development, the reference voltage should be impressed from outside.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET Reset terminal (RESET) Initial reset can be executed externally by setting the reset terminal to the low level. Maintain a low level of 0.1 msec to securely perform the initial reset. When the reset terminal goes high, the CPU begins to operate. However, when turning the power on, the reset terminal should be set at a low level as in the timing shown in Figure 2.2.2. 2.2 V VDD 2.0 msec or more RESET Fig. 2.2.2 Initial reset at power on 0.4•VDD 0.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET If you use this function, make sure that the specified ports do not go low at the same time during ordinary operation. Furthermore, do not perform an initial reset when turning the power on by this function. Watchdog timer If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See Section 4.2, "Resetting Watchdog Timer" for details.
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CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C62740 employs the 4-bit core CPU S1C6200A for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200A. Refer to "S1C6200/6200A Core CPU Manual" for details about the S1C6200A. Note the following points with regard to the S1C62740: (1) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used.
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CHAPTER 3: CPU, ROM, RAM 3.3 RAM The RAM, a data memory storing a variety of data, has a capacity of 512 words, each of four bits. When programming, keep the following points in mind. (1) Part of the data memory can be used as stack area when subroutine calls and saving registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words of the stack area.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C62740 are memory mapped, and interfaced with the CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access the I/O memory in the memory map. The following sections describe how the peripheral circuits operation. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Address Low F 0 1 2 3 4 5 6 7 8 9 A B C D E Page High M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 0 1 2 3 RAM (128 words x 4 bits) 4 R/W 5 6 7 0 8 Display memory (32 words x 4 bits) W 9 A Unused area B C D E I/O memory (56 words x 4 bits) F 0 1 2 3 RAM (128 words x 4 bits) 4 R/W 5 6 7 1 8 Display memory (32 words x 4 bits) W 9 A Unused area B C D E I/O memory (56 words x 4 bits) F Unused area Fig. 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) 4.2 Resetting Watchdog Timer Configuration of watchdog timer The S1C62740 incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 1 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3–4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2.1 is the block diagram of the watchdog timer. OSC1 demultiplier (256 Hz) Fig. 4.2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) Table 4.2.1 lists the watchdog timer's control bits and their addresses. Control of watchdog timer Table 4.2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit Configuration of oscillation circuit The S1C62740 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C62740 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) OSC3 oscillation circuit The S1C62740 has twin clock specification. The mask option enables selection of either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's sub-clock.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) Control of oscillation circuit Table 4.3.1 lists the control bits and their addresses for the oscillation circuit. Table 4.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) Clock frequency and instruction execution time Table 4.3.2 Clock frequency and instruction execution time Programming notes Table 4.3.2 shows the instruction execution time according to each frequency of the system clock. Clock frequency Instruction execution time (µsec) 5-clock instruction 7-clock instruction 12-clock instruction OSC1: 32.768 kHz OSC3: 1 MHz 152.6 5.0 213.6 7.0 366.2 12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00–K03, K10) Configuration of input ports The S1C62740 has five bits general-purpose input ports. Each of the input port terminals (K00–K03, K10) provides internal pull up resistor. Pull up resistor can be selected for each bit with the mask option. Figure 4.4.1 shows the configuration of input port. Interrupt request Mask option Kxx Data bus VDD Address Fig. 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) All five bits of the input ports (K00–K03, K10) provide the interrupt function. The conditions for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected individually for all five bits by the software. Interrupt function (1) K00–K03 interrupt Figure 4.4.2 shows the configuration of K00–K03 interrupt circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Interrupt selection register SIK03 SIK02 SIK01 SIK00 1 1 1 0 Input comparison register DFK03 DFK02 DFK01 DFK00 1 0 1 0 With the above setting, the interrupt of K00–K03 is generated under the following condition: (1) K03 1 (2) K03 1 (3) K03 0 (4) K03 0 Input port K02 K01 0 1 ↓ K02 K01 0 1 ↓ K02 K01 0 1 ↓ K02 K01 1 1 Fig. 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) (2) K10 interrupt Figure 4.4.4 shows the configuration of K10 interrupt circuit. K10 Address Data bus Address Input comparison register (DFK10) Interrupt factor flag (IK1) SLEEP cancellation Interrupt request Address Interrupt mask register (EIK1) Address Fig. 4.4.4 Input interrupt circuit configuration (K10) The input port K10 can generate interrupts for systems other then K00–K03.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Table 4.4.1 lists the input ports control bits and their addresses. Control of input ports Table 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) DFK00–DFK03, DFK10: Interrupt conditions for terminals K00–K03 and K10 can be set Input comparison registers with these registers. (D2H, D3H•D0) When "1" is written: Falling edge When "0" is written: Rising edge Reading: Valid The interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00–K03 and K10), through the input comparison registers (DFK00–DFK03 and DFK10).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) These flags are reset when the software reads them. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. At initial reset, these flags are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00–R03) Configuration of output ports The S1C62740 has four bits general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Nch open drain output. Further, each of the output port to be used as special output ports by the software setting. Figure 4.5.1 shows the configuration of the output port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ Register BZR03 R03 (BZ) Register R03 Data bus Register BZR02 R02 (BZ) Register R02 PTOVF Register PTR01 R01 (PTOVF) Register R01 FOUT Register FOR00 R00 (FOUT) Register R00 Fig. 4.5.2 Structure of the output ports R00–R03 • BZ and BZ BZ and BZ are the buzzer signal output for driving the piezo(R02 and R03) electric buzzer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) • FOUT By setting the register FOR00 to "1", R00 is set to FOUT (clock) (R00) output port. When FOR00 is set to "0", R00 become the regular DC output port. When the FOUT output is selected, ON/OFF of the signal output can be controlled by the R00 register. The frequency of clock output signal may be selected from among 4 types as Table 4.5.2 by setting of the FOFQ0 and FOFQ1 registers. Table 4.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Table 4.5.3 lists the output ports' control bits and their addresses. Control of output ports Table 4.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) When the PTOVF output is selected, ON/OFF of the signal output can be controlled by the R01 register. At initial reset, this register is set to "0". BZR02, BZR03: Selects the output type R02, R03 output selection When "1" is written: register When "0" is written: (E0H•D2, D3) Reading: for the R02 and R03 terminals.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 Controls the FOUT (clock) output. (when FOUT is selected): When "1" is written: High level (DC) output Special output port data When "0" is written: Clock output (D4H•D0) Reading: Valid FOUT output can be controlled by writing data to R00. At initial reset, this register is set to "1". FOFQ0, FOFQ1: Selects the FOUT frequency. FOUT frequency selection FOFQ1 FOFQ0 register 1 1 (E1H•D0, D1) 1 0 0 1 Table 4.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00–P03, P10–P13, P20–P23) Configuration of I/O ports The S1C62740 has 12 bits (4 bits × 3) general-purpose I/O ports. Figure 4.6.1 shows the configuration of the I/O port. The four bits of each of the I/O ports P00–P03, P10–P13 and P20– P23 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) I/O control registers and input/output mode Input or output mode can be set for the four bits of I/O ports P00– P03, P10–P13 and P20–P23 by writing data into the corresponding I/O control register IOC0, IOC1 and IOC2. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Control of I/O ports Table 4.6.1 lists the I/O ports' control bits and their addresses. Table 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) When PUP register is set to "1", the built-in pull up resistor goes ON during input mode, so that the I/O port terminal is pulled up. Internal pull up resistors are only ON during input mode, but the gate floating has not occur even during output mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) PUP0, PUP1, PUP2: The pull up during the Pull up control register When "1" is written: (D7H•D0–D2) When "0" is written: Reading: input mode can be set with these registers. Pull up ON Pull up OFF Valid The built-in pull up resistor which is turned ON during input mode is set to enable in units of four bits. PUP0, PUP1 and PUP2 set the pull up for P00–P03, P10–P13 and P20–P23, respectively.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7 LCD Driver (COM0–COM3, SEG0–SEG31) Configuration of LCD driver The S1C62740 has four common terminals (COM0–COM3) and 32 segment terminals (SEG0–SEG31), so that it can drive an LCD with a maximum of 128 (32 × 4) segments. The power for driving the LCD is generated by the CPU internal circuit so that there is no need to apply power especially from outside.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 COM2 LCD lighting status COM0 COM1 COM2 COM3 SEG0–31 COM3 VC3 VC2 VC1 VSS Not lit Lit SEG0 –SEG31 Fig. 4.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0–31 COM2 Not lit Lit COM3 VC3 VC2 VC1 VSS SEG0 –SEG31 Fig. 4.7.2 Drive waveform for 1/3 duty Frame frequency VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0–31 COM2 COM3 VC3 VC2 VC1 VSS Not lit Lit SEG0 –SEG31 Fig. 4.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD display ON/OFF control and duty switching (1) Display ON/OFF control In the S1C62740, ON/OFF of the LCD display can be controlled by LCDON register. At initial reset, LCDON is set to "0", and the LCD display is set to the OFF status. In this time, the COM terminal and the SEG terminal goes to VC1 level. To set the LCD display ON, write "1" to register LCDON.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) The LCD driver has a segment decoder built-in, and the data bit of the optional address in the display memory area (80H–9FH) can be allocated to the optional segment. This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Output specification ➀ The segment terminals (SEG0–SEG31) are selected with the mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment terminal is output. ➁ When DC output is selected, either complementary output or Nch open drain output can be selected for each terminal with the mask option.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LDTY1, LDTY0: Sets the LCD drive duty as shown in Table 4.7.3 LCD drive duty selection (EFH•D3, D2) LDTY1 LDTY0 Duty Terminals used Maximum number in common Table 4.7.3 LCD drive duty setting 0 0 1 1 0 1 0 1 1/4 1/3 1/2 1/1 COM0–COM3 COM0–COM2 COM0, COM1 COM0 of segments Frame frequency * 128 (32 × 4) fOSC1/1,024 (32 Hz) 96 (32 × 3) fOSC1/768 (42.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8 Clock Timer The S1C62740 has a built-in clock timer as the source oscillator for OSC1 (crystal oscillator). The clock timer is configured of a 8-bit binary counter that serves as the input clock, a 256 Hz signal output by the OSC1 oscillation circuit. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software. Figure 4.8.1 is the block diagram for the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.2 is the timing chart of the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.8.1 shows the clock timer control bits and their addresses. Control of clock timer Table 4.8.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) IT32, IT8, IT2, IT1: These flags indicate the status of the clock timer interrupt. Interrupt factor flag When "1" is read: Interrupt has occurred (C6H) When "0" is read: Interrupt has not occurred Writing: Invalid The interrupt factor flags (IT32, IT8, IT2, IT1) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock timer interrupt.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Programming notes (1) Be sure to data reading in the order of low-order data (TM0– TM3) then high-order data (TM4–TM7). (2) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Consequently, perform flag reading (reset the flag) as necessary at reset. (3) When the clock timer has been reset, the watchdog timer is also reset.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.9 Stopwatch Timer Configuration of stopwatch timer The S1C62740 has a 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz signal (signal obtained by approximately demultiplying the 256 Hz signal output by the oscillation circuit). Data can be read out four bits at a time by the software. Figure 4.9.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) Count-up pattern The stopwatch timer is configured of four-bit BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal. Figure 4.9.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) Interrupt function The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWL and SWH respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.9.3 is the timing chart for the stopwatch timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) Control of stopwatch timer Table 4.9.1 list the stopwatch timer control bits and their addresses. Table 4.9.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) EISW0, EISW1: These registers are used to select whether to mask the stopwatch Interrupt mask register timer interrupt. (CBH•D0, D1) When "1" is written: Enabled When "0" is written: Masked Reading: Valid The interrupt mask registers (EISW0, EISW1) are used to separately select whether to mask the 10 Hz and 1 Hz interrupts. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWRUN: This bit controls RUN/STOP of the stopwatch timer. Stopwatch timer RUN/STOP When "1" is written: RUN (E6H•D1) When "0" is written: STOP Reading: Valid The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10 Programmable Timer S1C62740 has a programmable timer which is configured with an 8 bits pre-settable down counter. Aside from the count by the built-in clock (fOSC1/fOSC3), this programmable timer also possesses an event counter function that performs counting by making the signal input from the input port K10 the clock.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) In case such as when counting by a key input, this causes it to eliminate noise of 2 msec or less such as chattering and to accept signals of 6 msec or more. (Acceptance of signals within the range from 2 msec to 6 msec is uncertain.) The K10 input (direct) is bypassed by this noise reject circuit. When it inputs a clock of 6 msec or less, you should select direct.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) (2) Data reload The reload register (8 bits) for the initial value setting of the down counter is built into the programmable timer. The data set into the reload register is loaded into the down counter in the following instances and the count down is done from that value. 1. When the programmable timer has been reset by software 2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) Interrupt function The programmable timer generates interrupt after the down-count from the initial setting is completed and the content of the downcounter indicates 00H. After interrupt generation, the programmable timer reloads the initial count value into the down-counter and resumes counting. Figure 4.10.4 shows the timing chart of the programmable timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) Table 4.10.3 list the stopwatch timer control bits and their addresses. Control of programmable timer Table 4.10.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) PTD0, PTD1: Selects the dividing ratio in the predivider for the input clock. Dividing ratio selection PTD1 PTD0 Dividing ratio (EAH•D2, D3) 0 0 1/256 0 1 1/32 Table 4.10.5 1 0 1/4 Clock dividing ratio selection 1 1 1/1 At initial reset, these registers are set to "0". RD0–RD3, RD4–RD7: These are reload registers for setting the initial value of the timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) PT0–PT3, PT4–PT7: Will read the data from the down-counter of the programmable Programmable timer data timer. (EBH, ECH) Will read the low-order 4 bits of the 8 bits counter data PT0–PT3, and the high-order 4 bits PT4–PT7. Because these 8 bits are only for reading, writing operation is rendered invalid. At initial reset, timer data will be undefined.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) IPT: This is the interrupt factor flag of the programmable timer. Interrupt factor flag When "1" is read: Interrupt has occurred (C0H•D0) When "0" is read: Interrupt has not occurred Writing: Invalid From the status of this flag, the software can decide whether the programmable timer interrupt. Note, however, that even if the interrupt is masked, this flag will be set to "1" by the counter value will become "00H".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY) Configuration of serial interface The S1C62740 has a synchronous clock type 8 bits serial interface built-in. The configuration of the serial interface is shown in Figure 4.11.1. The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Master mode and slave mode of serial interface The serial interface of the S1C62740 has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates this internal clock at the SCLK (P22) terminal and controls the external (slave side) serial device.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Data input/output and interrupt function The serial interface of S1C62740 can input/output data via the internal 8 bits shift register. The shift register operates by synchronizing with either the synchronous clock output from SCLK (P22) terminal (master mode), or the synchronous clock input to SCLK (P22) terminal (slave mode). The serial interface generates interrupt on completion of the 8 bits serial data input/output.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) Timing chart The S1C62740 serial interface timing chart is shown in Figure 4.11.4. SCTRG SCLK SIN 8-bit shift register SOUT ISIO SRDY (slave mode) (high) SRDY (master mode) Fig. 4.11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Table 4.11.2 list the serial interface control bits and their addresses. Control of serial interface Table 4.11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) PUP2: Sets the pull up of SIN Pull up control register mode). (D7H•D2) When "1" is written: When "0" is written: Reading: terminal and SCLK terminal (in the slave Pull up ON Pull up OFF Valid Sets the pull up resistor built into the SIN (P20) and SCLK (P22) ports to ON or OFF. SCLK pull up is effective during the slave mode. At initial reset, this register is set to "0" and pull up goes OFF.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCTRG: This is a trigger to start input/output of synchronous clock. Clock trigger When "1" is written: Trigger (DCH•D0) When "0" is written: No operation Reading: Always "0" When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed prior to writing "1" to SCTRG.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) EISIO: This is the interrupt mask register of the serial interface. Interrupt mask register When "1" is written: Enabled (C8H•D1) When "0" is written: Masked Reading: Valid With this register, masking of the serial interface interrupt can be selected. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Programming notes (1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 ↔ fOSC3) while the serial interface is operating. (2) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 4.12 A/D Converter Configuration of A/D converter The S1C62740 has a built-in dual slope type A/D converter. This A/D converter has 5 analog input terminals and voltage, differential voltage between two terminals and resistance can be measured by specifying combinations with those terminal functions using software. The resolution and conversion time of the four types indicated below can be set by programs.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Measured input terminal and measurement items Five analog input terminals AI0–AI4 have been set in the A/D converter. VIN VR -VR AIF + BUF – S11 S12 S13 S10 BF S14 GND S2 AI0 AI1 S4 AI2 Fig. 4.12.2 Analog input terminal configuration To non inverted input of integral AMP S3 VR, -VR generation circuit S5 AI3 S6 AI4 VR2 GND VR1 It offers the following three type of measurements.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Since the input voltage of each terminal is limited to a maximum of ±320 mV, when measuring voltage that is likely to exceed this range, you should input a voltage that has been voltage divided to less than ±320 mV. R1 AIx VAI Fig. 4.12.4 Attenuator circuit when it exceeds ±320 mV VIN R2 VIN = GND GND R2 VAI R1 + R2 (2) Differential voltage measurement • Measurement terminal: AI0–AI1 and AI2–AI3 • Input voltage: Max.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) In this mode, the A/D converter measures the resistance value by connecting elements as the follows: 1. Connects measured resistance such as a thermistor or other elements between AI2 and GND terminals or between AI3 and GND terminals 2. Connects a reference resistance where resistance value does not change due to such factors as the temperature between AI4 and AI2 terminals or between AI4 and AI3 terminals 3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) The A/D converter of the S1C62740 has a built-in reference voltage generation circuit and it generates a reference voltage VR1 for resistance measurement and a reference voltage VR2 for voltage measurement. VR1 and VR2 may also be adjusted from outside. Use of the external adjustment or the internal adjustment can be selected by the mask option. In addition, VR1 can be impressed from outside.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (≈ -475.0 mV) + VR1 – 19 kΩ 20 kΩ VRA 15 kΩ ~1.5 MΩ (≈ -163.8 mV) Fig. 4.12.8 External adjustment for VR1 andVR2 0.1 µF GND VR2 VRON = "1" VRAON = "0" 10 kΩ GND (4) External impression on VR1 When a high precision voltage from a built-in reference voltage is necessary, you can impress an external voltage onto the VR1 terminal. In this case, select the external adjustment mode by the mask option.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Middle electric potential (GND) generation circuit As shown in Figure 4.12.10, it outputs an middle electric potential (GND) through the operational amplifier buffer that divides the source voltage impressed between VDDA–VSSA into 1/2 by means of a resistance. This GND becomes the reference potential of the A/D converter. VDD/VDDA + + GND 3.3 µF – + Fig. 4.12.10 Middle electric potential (GND) generation circuit configuration 3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Operation of the dual slope type A/D converter Figure 4.12.12 shows the circuit diagram of the dual slope type A/ D converter built into S1C62740. BF VIN VR -VR RI CI CO S1 + BUF – S2 + INT – GND Fig. 4.12.12 Circuit diagram of A/D converter CAZ + CMP – GND To A/D converter control circuit S3 This A/D converter performs A/D conversion according to the following three sequences.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) • Positive input voltage Buffer AMP output voltage GND Integral AMP output GND Auto zero adjustment Input integration Auto zero adjustment *2 *1 Comparator output Reverse integration *3 GND *1: This voltage is proportional to input *2: Time is proportional to input voltage *3: The gradient is fixed • Negative input voltage Buffer AMP output voltage Integral AMP output Fig. 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) The slope of this integral output waveform changes in proportion to the input voltage. The portion charged into the CAZ due to the previous auto zero adjustment is added to the input voltage of the integral AMP and negates the offset voltage. The input integration period becomes the time that has been counted for only 1/2 the number resolution counts that have specified the 32 kHz clock.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Since the slope of the reverse integral waveform is fixed, the counter value according to the integral result of the input voltage in step (2) is obtained from the dual slope counter. The counter value n at this time is indicated by the following expression. 0 = Vint - (-VR * n * T / CI * RI) (Expression 4.12.2) According to Expression 4.12.1 and Expression 4.12.2, it becomes n = VIN * N / VR (Expression 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) • Resistance measurement mode At the time of resistance measurement, the non-inverted input of the integral AMP is set to the GND level. As shown in Figure 4.12.15, a voltage drop of the reference resistance is obtained as the reference voltage at the time of resistance measurement by impressing a VR1 voltage from the AI4 terminal onto the reference resistance connected between the AI4–AI3 (or AI2) terminals.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) A/D conversion and interrupt Here we will explain about the control and interrupt of the A/D conversion and reading of data. Before beginning A/D conversion, it is necessary to set the analog input terminal and measurement items explained previously and set the reference voltage generation circuit and middle electric potential generation circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (3) Wait time for A/D conversion To perform a stable A/D conversion, the following wait times are necessary. • In the case of voltage measurement mode and differential voltage measurement mode Take 300 msec or more wait time from the beginning of the reference voltage VR1 generation or impressing from outside to the end of an input integration period. (Satisfy the regulation time by delaying the timing of the A/D converter ON.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Take care that conversion data may sometime become invalid by turning the A/D converter OFF (including resetting). In this case, as it is "0" the IDR is not set. When reading data after turning the A/D converter OFF, the A/D converter should be OFF in the period from an interrupt generation to the beginning of a reverse integration. You should process the read data using software, such that is becomes the object volume.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) A/D conversion 1 Measurement mode and input terminal setting Read Reference voltage generation circuit setting Read Middle electric potential generation circuit setting Read IDR IDR = "0" Start A/D conversion (Set ADON to "1") Yes 2 No No Data processing A/D interrupt Yes 2 No Read Complete Yes Read Stop A/D conversion (Set ADON to "0") 1 END Fig. 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Control of the A/D converter Table 4.12.4 shows the A/D converter control bit and its address. Table 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) GNDON0, GNDON1: Control the middle electric potential generation circuit as shown in GND generation circuit control Table 4.12.5. (F0H•D3, D2) Table 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) ADRS0, ADRS1: Selects the A/D conversion resolution (number of counts). Resolution selection ADRS1 ADRS0 Resolution Conversion time (F3H•D0, D1) 0 0 6,552 counts 500 msec 0 1 3,276 counts 250 msec 1 0 1,638 counts 125 msec Table 4.12.6 Resolution selection 1 1 820 counts 62.5 msec At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) AD0–AD12: The A/D conversion result counted by the dual slope counter is A/D conversion data binary data. (F7H, F8H, F9H, FAH•D0) This data is effective from the time when the reverse integration period has terminated (when an interrupt has been generated) until the next reverse integration period has been terminated and during this time it reads in the order of the address F7H→F8H→F9H→FAH. At initial reset, these data is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) IAD: This flag indicates interrupt caused by the A/D converter. Interrupt factor flag When "1" is read: Interrupt has occurred (C4H•D0) When "0" is read: Interrupt has not occurred Writing: Invalid From the status of this flag, the software can decide whether an A/ D interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (General-purpose Operation Amplifier) 4.13 General-purpose Operation Amplifier (AMP) Configuration of AMP circuit The S1C62740 has an MOS input general-purpose operation amplifier built into two channels (AMP0 and AMP1). The respective AMP, which has two differential input terminals (inverted input terminal AIM, noninverted input terminal AIP) and output terminal (AOUT), can be used for general purposes.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (General-purpose Operation Amplifier) Table 4.13.1 lists the analog comparator control bits and their addresses. Control of AMP circuit Table 4.13.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.14 SVD (Supply Voltage Detection) Circuit Configuration of SVD circuit The S1C62740 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be controlled through the software. Figure 4.14.1 shows the configuration of the SVD circuit. VDDA SVDDT SVDON VSSA Criteria voltage setting circuit Fig. 4.14.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. ➀ ➁ ➂ ➃ Set SVDON to "1" Maintain for 100 µsec minimum Set SVDON to "0" Read SVDDT However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there is no need to worry about maintaining 100 µsec for SVDON = "1" in the software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) SVDDT: This is the result of SVD data When "0" is read: (FFH•D1) When "1" is read: Writing: supply voltage detection. Supply voltage (VDDA–VSSA) ≥ Criteria voltage Supply voltage (VDDA–VSSA) < Criteria voltage Invalid The result of supply voltage detection at time of SVDON is set to "0" can be read from this register. At initial reset, SVDDT is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.15 Interrupt and HALT/SLEEP The S1C62740 provides the following interrupt settings, each of which is maskable.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) IPT EIPT ISIO EISIO K10 IK1 DFK10 SLEEP cancellation EIK1 K00 DFK00 Interrupt vector generation circuit SIK00 K01 Program counter (low-order 4 bits) DFK01 SIK01 IK0 K02 EIK0 DFK02 SIK02 K03 INT (interrupt request) DFK03 SIK03 Interrupt flag IAD EIAD ISW1 EISW1 ISW0 Interrupt factor flag EISW0 Interrupt mask register IT1 EIT1 Input comparison register IT2 Interrupt selection register EIT2 IT8 EIT8 IT32 Fig. 4.15.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) Table 4.15.1 shows the factors for generating interrupt requests. Interrupt factor The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.15.2 shows the correspondence between interrupt mask registers and interrupt factor flags.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. Interrupt vector ➀ The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) Tables 4.15.4(a) and (b) show the interrupt control bits and their addresses. Control of interrupt Table 4.15.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) Table 4.15.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) Programming notes (1) When it shifts to the SLEEP status, you must invariably set the K10 interrupt to enable. (2) When shifting to the SLEEP status, the CPU clock must be set to OSC1 and the OSC3 oscillation circuit must be off. (3) The interrupt factor flags are set when the timing condition is established, even if the interrupt mask registers are set to "0".
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CHAPTER 5: SUMMARY OF NOTES CHAPTER 5 SUMMARY OF NOTES 5.1 Notes for Low Current Consumption The S1C62740 contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 5.1.
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CHAPTER 5: SUMMARY OF NOTES 5.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these area. Watchdog timer The watchdog timer must be reset within 3-second cycles.
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CHAPTER 5: SUMMARY OF NOTES I/O ports When in the input mode, I/O ports are changed from low to high by pull up resistor, the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression.
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CHAPTER 5: SUMMARY OF NOTES (2) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (3) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0–SD7.
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CHAPTER 5: SUMMARY OF NOTES However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there is no need to worry about maintaining 100 µsec for SVDON = "1" in the software. (2) The SVD circuit should normally be turned OFF as the consumption current of the IC becomes large when it is ON. Interrupt and HALT/ (1) When it shifts to the SLEEP status, you must invariably set the K10 interrupt to enable.
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CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS CHAPTER 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS • For temperature measurement by connecting thermistor (VR1, VR2 and GND: internal voltage) SEG0 | SEG31 COM0 | COM3 LCD panel K00 | K03 K10 P00 | P03 P10 | P13 P20 (SIN) P21 (SOUT) P22 (SCLK) P23 (SRDY) C1 C2 CC CB CA VDD VDDA TEST CP1 +3 V VSS VSSA VCA S1C62740 RA2 RA1 VC1 VC2 VC3 OSC1 OSC2 VD1 OSC3 AIP0 AIM0 AOUT0 AIP1 AIM1 AOUT1 X'tal CR C3 C4 C5 CGX C6 CGC *1 *2 C7 R02(BZ) + C8 CIF
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CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS X'tal CGX CR CGC CDC RCR RA1 RA2 TH RREF RI Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitance Drain capacitance Resistance for CR oscillation Resistance for LCD drive voltage adjustment Resistance for LCD drive voltage adjustment Thermistor Reference resistance for resistance measurement Integral resistance CI CAZ CIF C1–C9 CP1, CP2 Integral capacitor Capacitor for auto zero adjustment Analog input filter capacitor 32.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Rating Item (VSS = 0 V) Symbol Rated value -0.5 to 7.0 Unit V Power voltage VDD Input voltage (1) Input voltage (2) VI -0.5 to VDD + 0.3 V VIOSC -0.5 to VD1 + 0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics If no special requirement VDD = 3 V, VSS = 0 V, fOSC1 = 32.768 kHz, Ta = 25°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.1 µF Item High level input voltage (1) Symbol VIH1 Condition K00~03, K10 Min. 0.8·VDD Typ. Max. Unit VDD V V V P00~03, P10~13 P20~23, SIN, SCLK High level input voltage (2) Low level input voltage (1) VIH2 RESET, TEST 0.9·VDD VDD VIL1 K00~03, K10 0 0.2·VDD 0 0 0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Characteristics and Consumed Current If no special requirement VDD = VDDA = 3 V, VSS = VSSA = 0 V, fOSC1 = 32.768 kHz, CG = 25 pF, Ta = 25°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.1 µF Item LCD drive voltage Symbol Condition VCA = VC1, IC1 = -5 µA VC1 Min. 0.95 VC2 SVDS = "0" SVDS = "1" 2·VC1 x 0.9 3·VC1 x 0.9 2.5 2.4 2.6 2.5 SVDS = "2" SVDS = "3" 2.3 2.2 2.4 2.3 2.5 2.4 100 V V µS 0.7 2.0 6.0 200 2.0 7.0 15.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS A/D converter If no special requirement VDD = VDDA = 3 V, VSS = VSSA = 0 V, fOSC1 = 32.768 kHz, CG = 25 pF, Ta = 0 to 50°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS [Refference curves] Absolute error E Zero point error EZ Count (+) Count (+) Measured value E Ideal value (+) Input (–) Input (–) E = measured value - ideal value E (+) EZ EZ = value counted when 0 mV is input (–) (–) * There is no standard in the resistance measurement mode because 0 mV input has been inhibited.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS Reference voltage generation circuit If no special requirement VDD = VDDA = 3 V, VSS = VSSA = 0 V, fOSC1 = 32.768 kHz, CG = 25 pF, Ta = 25°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.1 µF Item Output voltage (1) Output voltage (2) Input voltage Symbol Condition VR1O GND reference, Internal adjustment mode VRON = VRAON = "1" VR2O GND reference, Internal adjustment mode VRON = VRAON = "1" VR1I GND reference, External adjustment mode Min. Typ. Max.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS Middle electric potential (GND) generation circuit If no special requirement VDD = VDDA = 3 V, VSS = VSSA = 0 V, fOSC1 = 32.768 kHz, CG = 25 pF, Ta = 25°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.1 µF Item Symbol Condition Output voltage GNDO GNDON = "01, 10, 11" Input voltage GNDI GNDON = "00" Input current IGND  GNDON = "00", A/D related are all OFF. Min. Typ. Max. Unit VDDA/2 -0.05 VDDA/2 VDDA/2 VDDA/2 +0.05 VDDA/2 V VDDA/2 -0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS General-purpose operational amplifier If no special requirement VDD = VDDA = 3 V, VSS = VSSA = 0 V, fOSC1 = 32.768 kHz, CG = 25 pF, Ta = 25°C, VD1, VC1, VC2 and VC3 are internal voltage, C1–C6 = 0.1 µF Item High level output voltage Low level output voltage High level output current Low level output current Offset voltage Input voltage range Slew rate Response time Power current consumption Symbol Condition Min. VOHA AMPONx = "1", VAIM = GND 0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values.
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CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE 8.1 Plastic Package QFP5-100pin (Unit: mm) 25.6 ± 0.4 20.0 ± 0.1 80 51 ± 0.1 ± 0.4 19.6 50 14.0 81 Index 100 31 0.65 0.30 ± 0.1 30 2.7 ± 0.1 0.15 ± 0.05 1 1.5 ± 0.3 2.
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CHAPTER 8: PACKAGE QFP15-100pin (Unit: mm) 16.0 ±0.4 14.0 ±0.1 75 51 16.0 ±0.4 50 14.0 ±0.1 76 Index 100 26 1 25 0.18 ±0.1 1.7max 0.125 0.5 0.5 ±0.2 1.
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CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples (Unit: mm) 26.8 20.0 51 50 100 31 14.0 81 30 0.4 0.76 0.30 0.95 0.65 0.8 1 20.9 80 Grass Note: The ceramic package is fixed in this form regardless selecting of the plastic package form.
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CHAPTER 9: PAD LAYOUT CHAPTER 9 PAD LAYOUT 9.1 Diagram of Pad Layout 25 20 15 10 5 1 109 30 105 35 100 40 (0, 0) X 95 5.5 mm Y 45 90 50 85 60 65 70 75 80 55 5.
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CHAPTER 9: PAD LAYOUT 9.2 Pad Coordinates (Unit: µm) Pad No. I-134 X Y Pad No. Pad name X X Y 1 Pad name N.C. 2,512 2,586 38 SEG22 -2,512 526 75 VRA 1,004 -2,586 2 N.C.
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Software II.
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CONTENTS CONTENTS CHAPTER 1 INTRODUCTION ............................................................... II-1 CHAPTER 2 BLOCK DIAGRAM ........................................................... II-2 CHAPTER 3 PROGRAM MEMORY (ROM) .......................................... II-3 CHAPTER 5 CHAPTER 6 Configuration of the ROM ........................................................ II-3 3.2 Interrupt Vector ........................................................................ II-3 DATA MEMORY ....
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CONTENTS 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23) ........................ II-27 I/O data memory of the I/O ports ...................................... Control of the I/O ports ...................................................... Example program for the I/O ports .................................... Serial I/O port ................................................................... Programming notes ............................................................ 6.6 LCD Driver ......................
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CONTENTS 6.14 Sleep ....................................................................................... II-65 I/O data memory of sleep function ..................................... Control of the sleep function .............................................. Example program for the sleep function ............................. Programming notes ............................................................ II-65 II-65 II-66 II-68 6.15 Interrupt ...........................................................
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CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION The S1C62740 is a microcomputer with a C-MOS 4-bit core CPU S1C6200A as main component, and dual slope A/D converter 4,096 steps × 12 bits ROM, 512 words × 4 bits RAM, programmable timer, clock timer, clock synchronous serial interface, etc. built-in. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of application, and is especially suitable for battery-driven system.
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CHAPTER 2: BLOCK DIAGRAM CHAPTER 2 BLOCK DIAGRAM The S1C62740 block diagram is shown in Figure 2.1. S1C62740 BLOCK DIAGRAM OSC1 OSC2 OSC3 OSC4 CORE CPU S1C6200A ROM 4,096 x 12 OSC and SLEEP SYSTEM RESET CONTROL RAM 512 x 4 COM0– COM3 SEG0– SEG31 V DD V CA V C1 V C2 V C3 CA CB CC V D1 V SS AIP0, 1 AIM0, 1 AOUT0, 1 V DDA V RA V R1 V R2 CH CL GND V SSA Fig. 2.
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CHAPTER 3: PROGRAM MEMORY (ROM) CHAPTER 3 PROGRAM MEMORY (ROM) 3.1 Configuration of the ROM S1C62740 is built-in with 4,096 steps × 12 bits mask ROM for program storage. The program area is 16 (0–15) pages, each 256 (00H–FFH) steps. After initial reset, the program beginning address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 02H–0FH. The configuration of the ROM is as shown in Figure 3.1.1.
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CHAPTER 4: DATA MEMORY CHAPTER 4 DATA MEMORY 4.1 Configuration of the Data Memory The data memory consist of 512 words RAM, and I/O memory which controls the peripheral circuit. Figure 4.1.1 show the configuration of the data memory. When you make your program, please take note of the following: (1) Since the stack area is taken from the RAM area, take care that destruction of stack data due to data writing does not occur. Sub-routine calls or interrupts consume 3 words of the stack area.
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CHAPTER 4: DATA MEMORY Address Low F 0 1 2 3 4 5 6 7 8 9 A B C D E Page High M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 0 1 2 3 RAM (128 words x 4 bits) 4 R/W 5 6 7 0 8 Display memory (32 words x 4 bits) W 9 A Unused area B C D E I/O memory (56 words x 4 bits) F 0 1 2 3 RAM (128 words x 4 bits) 4 R/W 5 6 7 1 8 Display memory (32 words x 4 bits) W 9 A Unused area B C D E I/O memory (56 words x 4 bits) F Unused area Fig. 4.1.
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CHAPTER 4: DATA MEMORY 4.2 Detail Map of the I/O Memory Tables 4.2.1(a)–(d) show the detail map of the I/O memory. Table 4.2.
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CHAPTER 4: DATA MEMORY Table 4.2.
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CHAPTER 4: DATA MEMORY Table 4.2.
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CHAPTER 4: DATA MEMORY Table 4.2.
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CHAPTER 5: INITIAL RESET CHAPTER 5 INITIAL RESET 5.1 Initialized Status The CPU core and peripheral circuits are initialized by initial resetting as follows: Table 5.1.
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CHAPTER 5: INITIAL RESET 5.2 Example Program for the System Initialization Following program shows the example of the procedure for system initialization.
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CHAPTER 5: INITIAL RESET LDPY LDPY CP JP MY,0H MY,0H XH,08H C,CLR2 ;CONTINUE TILL 080H ; ;* INITIALIZE PERIPHERAL CIRCUITS ; RSTCM: LD X,0E2H ;RESET CLOCK TIMER OR MX,0001B ; : ; 5.3 Programing Note for the System Initialization In some of initial registers and initial data memory area, the initial value is undefined after reset. Set them proper initial values by the program, as necessary.
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CHAPTER 6: PERIPHERAL CIRCUITS (Watchdog Timer) CHAPTER 6 PERIPHERAL CIRCUITS 6.1 Watchdog Timer I/O data memory of the watchdog timer The control registers of the watchdog timer is shown in Table 6.1.1. Table 6.1.
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CHAPTER 6: PERIPHERAL CIRCUITS (Watchdog Timer) Example program for the watchdog timer Following program shows the reset procedure for watchdog timer. Programing notes (1) The watchdog timer must be reset within 3-second cycles. Because of this, the watchdog timer data (WD0, WD1) cannot be used for clocking of 3 seconds or more.
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CHAPTER 6: PERIPHERAL CIRCUITS (OSC3) 6.2 OSC3 S1C62740 has two built-in oscillation circuits (OSC1 and OSC3). I/O data memory of the OSC3 The control registers of the OSC3 are shown in Table 6.2.1. Table 6.2.
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CHAPTER 6: PERIPHERAL CIRCUITS (OSC3) OR RET MX,CLKCHG ;CHANGE CLOCK TO OSC3 ; OS1: ;* CHANGE CLOCK FRWQUENCY FROM OSC3 TO OSC1 LD X,ZOSCC ;CHANGE CLOCK TO OSC1 AND MX,(NOT CLKCHG) AND 0FH ;CHANGE CLOCK TO OSC1 ; AND MX,(NOT OSCC) AND 0FH ;SET OSC3 TO OFF RET ; Programming notes (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes.
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CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports) 6.3 Input Ports (K00–K03 and K10) The control registers of the input ports are shown in Table 6.3.1. I/O data memory of the input ports Table 6.3.
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CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports) Control of the input ports Reading of input data Input data of the input port terminal may be read out with registers K00–K03 and K10. The terminal voltage of 5 bits input ports are each reading as "1" and "0" at high (VDD) level and low (VSS) level, respectively.
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CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports) Interrupt mask register EIK0 1 Interrupt selection register SIK03 SIK02 SIK01 SIK00 1 1 1 0 Input comparison register DFK03 DFK02 DFK01 DFK00 1 0 1 0 With the above setting, the interrupt of K00–K03 is generated under the following condition: (1) K03 1 (2) K03 1 (3) K03 0 (4) K03 0 Input ports K02 K01 0 1 ↓ K02 K01 0 1 ↓ K02 K01 0 1 ↓ K02 K01 1 1 K00 0 (Initial value) K00 1 K00 1 K00 1 Fig. 6.3.
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CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports) Example program for the input ports Following program shows the input ports controlling procedure.
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CHAPTER 6: PERIPHERAL CIRCUITS (Input Ports) ; : LD LD LD EI RET X,ZK0 Y,ZDFK0 MY,MX ;STORE DIFFERENTIAL REGISTER ; K1INT: ;* K1 INTERRUPT SERVICE ROUTINE ; LD X,ZIK1 LD A,MX ; : ; : LD X,ZK1 ;STORE DIFFERENTIAL REGISTER LD Y,ZDFK1 LD MY,MX EI RET ; Programming notes (1) When input ports are changed from low to high by pull up resistor, the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capacitance.
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CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports) 6.4 Output Ports (R00–R03) The control registers of the output ports are shown in Table 6.4.1. I/O data memory of the output ports Table 6.4.
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CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports) Example program for the general output ports Following program shows the output ports controlling procedure in ordinary DC output case.
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CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports) Control of the special use output ports In addition to the regular DC output, special output can be selected by software for output ports (R00–R03), as shown in Table 6.4.2. Pin name When special output is selected R00 R01 R02 R03 FOUT output PTOVF output BZ (buzzer) output BZ (buzzer inverted) output Table 6.4.2 Special output Figure 6.4.2 shows the structure of output ports (R00–R03).
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CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports) FOUT output The FOR00 is to select R00 for FOUT output. So when you want to use R00 as FOUT output, set FOR00 to "1", and R00 to "0". When R00 is selected to FOUT output, it outputs the clock of fOSC3, fOSC1 or the demultiplied fOSC1. The clock frequency can be selected by registers FOFQ1 and FOFQ0, from the frequencies listed in Table 6.4.3. Table 6.4.
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CHAPTER 6: PERIPHERAL CIRCUITS (Output Ports) LD MX,1000B ;SELECT R00 FOR FOUT, ;AND SET 512 Hz FREQUENCY ; ; ;* PTOVF OUTPUT ; PTOVF: LD X,ZR0 AND MX,1101B LD X,ZPTC2 LD MX,1110B LD X,ZRDL LBPX MX,00H ; LD X,ZPTC1 OR MX,0001B OR MX,0010B OR MX,1000B ; Programming notes ;TURN OFF R01 OUTPUT PORT ;SELECT OSC1 = 32 KHz ;SET RELOAD REGISTER = (0,0) ;RESTORE PROGRAMMABLE TIMER ;RUN PROGRAMMABLE TIMER ;SELECT R01 AS PTOVF OUTPUT (1) When BZ, BZ, FOUT and PTOVF output are selected by software, a hazard may
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CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports) 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23) I/O data memory of the I/O ports The control registers of the I/O ports are shown in Table 6.5.1. Table 6.5.
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CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports) How to set as output Set "1" in the I/O port control register D6H, D0 (D1 for P1, D2 for P2) and the I/O port (P00–P03) is set as an output port. The state of the I/O port (P00–P03) is decided by the address D8H (D9H for P1, DAH for P2). This data is held by the register, and can be set regardless of the contents of the I/O control registers. (The data can be set whether I/O ports are input ports or output ports is read directly.
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CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports) Loading P00–P03 output data into A register Label Mnemonic/operand Comment ;* ;* I/O PORT ;* ;* LOADING P00-P03 OUTPUT DATA INTO A REGISTER ; ZIOC EQU 0D6H ;I/O PORT CONTROL REGISTER ZPUP EQU 0D7H ;I/O PORT PULL-UP CONTROL REGISTER ZP0 EQU 0D8H ;I/O PORT P00-P03 ; LD Y,ZPUP ;SET PULL-UP CONTROL ;REGISTER ADDRESS AND MY,1110B ;DISABLE P00-P03 PULL UP RESISTORS LD Y,ZIOC ;SET I/O PORT CONTROL ADDRESS OR MY,0001B ;SET P00-P03 AS OUTPUT PORT LD Y,ZP0 ;SET ADDRESS O
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CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports) Loading contents of B register into P00–P03 Label Mnemonic/operand Comment ;* ;* I/O PORT ;* ;* LOADING CONTENTS OF B REGISTER INTO P00-P03 ; ZIOC EQU 0D6H ;I/O PORT CONTROL REGISTER ZPUP EQU 0D7H ;I/O PORT PULL-UP CONTROL REGISTER ZP0 EQU 0D8H ;I/O PORT P00-P03 ; LD Y,ZPUP ;SET PULL-UP CONTROL REGISTER ADDRESS AND MY,1110B ;DISABLE P00-P03 PULL UP RESISTORS LD Y,ZIOC ;SET I/O PORT CONTROL ADDRESS OR MY,0001B ;SET P00-P03 AS OUTPUT PORT LD Y,ZP0 ;SET ADDRESS OF
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CHAPTER 6: PERIPHERAL CIRCUITS (I/O Ports) Serial I/O port The I/O port P20–P23 may be set by software as serial I/O port for the serial interface. P20: P21: P22: P23: Serial Serial Serial Serial interface interface interface interface data input port (SIN) data output port (SOUT) clock port (SCLK) inverted READY signal (SRDY) The function of serial interface is explained in Section 6.10. Programming notes (1) When P20–P23 is used as general I/O ports, set PFS to "0".
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CHAPTER 6: PERIPHERAL CIRCUITS (LCD Driver) 6.6 LCD Driver The control registers of the LCD driver are shown in Table 6.6.1. I/O data memory of the LCD driver Table 6.6.
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CHAPTER 6: PERIPHERAL CIRCUITS (LCD Driver) • LCD display ON/OFF is controlled by register LCDON (EFH•D0). Set LCDON to "1" to turn on LCD. Set LCDON to "0" to turn off LCD. Figure 6.6.2 is an example of the 7-segment LCD assignment. a f b g Address 90H e Fig. 6.6.2 7-segment LCD assignment 91H c Register D3 D2 D1 D0 d c g b f a e d In the assignment shown in Figure 6.6.2, the 7-segment display pattern is controlled by writing data to display memory addresses 90H and 91H.
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CHAPTER 6: PERIPHERAL CIRCUITS (LCD Driver) Displaying 7-segment The LCD display routine using the assignment of Figure 6.6.2 can be programmed as follows.
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CHAPTER 6: PERIPHERAL CIRCUITS (LCD Driver) Bit-unit operation of the display memory Data Address D3 Fig. 6.6.
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CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer) 6.7 Clock Timer The control registers of the clock timer are shown in Table 6.7.1. I/O data memory of the clock timer Table 6.7.
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CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer) However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. Clock timer timing chart Address Register Frequency D0 128 Hz D1 64 Hz D2 32 Hz D3 16 Hz D0 8 Hz D1 4 Hz D2 2 Hz D3 1 Hz E3H E4H 32 Hz interrupt request 8 Hz interrupt request 2 Hz interrupt request 1 Hz interrupt request Fig. 6.7.
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CHAPTER 6: PERIPHERAL CIRCUITS (Clock Timer) LD A,MX LD LD EI RET X,ZEIT ;SET TO TIMER MASK REGISTER MX,0100B ;ENABLE TIMER 2 Hz INTERRUPT ; ; ;* CLOCK TIMER INTERRUPT ; TMINT: LD X,ZIT ;LOAD TIMER INTERRUPT FLAG ;TO B REGISTER LD B,MX FAN B,0100B ;CHECK TIMER 2 Hz INTERRUPT FLAG JP Z,TMINT1 ;NO, THEN JMP LD X,ZTML ;SET TO TIMER DATA ADDRESS LDPX A,MX ;READ TIMER LOW INTO A REGISTER LD B,MX ;READ TIMER HIGH INTO B REGISTER ; : ; DO THE PROCEDURE FOR 2 Hz INTERRUPT SERVICE ; : TMINT1: EI RET ; Program
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CHAPTER 6: PERIPHERAL CIRCUITS (Stopwatch Timer) 6.8 Stopwatch Timer I/O data memory of the stopwatch timer The control registers of the stopwatch timer are shown in Table 6.8.1. Table 6.8.
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CHAPTER 6: PERIPHERAL CIRCUITS (Stopwatch Timer) Stopwatch timer interrupt The stopwatch timer interrupt is generated at the falling edge of the frequencies (10 Hz and 1 Hz). At this time, the corresponding interrupt factor flag (ISW0 and ISW1) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (EISW0 and EISW1).
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CHAPTER 6: PERIPHERAL CIRCUITS (Stopwatch Timer) SWINIT: LD OR X,ZSWCTL ;SET STOPWATCH CONTROL ;REGISTER ADDRESS MX,0001B ;WHEN RESET STOPWATCH ;THEN (SWL,SWH) WILL BECOME (0,0) ; DI LD LD X,ZISW A,MX LD LD X,ZEISW MX,0001B ;ENABLE STOPWATCH 10 Hz INTERRUPT LD OR X,ZSWCTL MX,0010B ;START THE STOPWATCH TIMER ;RESET INTERRUPT FLAG ; ; ; EI RET ; ;* STOPWATCH TIMER INTERRUPT ; SWINT: LD X,ZISW ;LOAD STOPWATCH INTERRUPT FLAG ;TO B REGISTER LD B,MX ; FAN B,0001B ;CHECK STOPWATCH 10 Hz ;INTERRUPT FLAG
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CHAPTER 6: PERIPHERAL CIRCUITS (Stopwatch Timer) Programming notes (1) Be sure to data reading in the order of low-order data (SWL0– SWL3) then high-order data (SWH0–SWH3). (2) When the stopwatch timer has been reset, the interrupt factor flag (ISW) may sometimes be set to "1". Consequently, perform flag reading (reset the flag) as necessary at reset. (3) Write the interrupt mask register (EISW) only in the DI status (interrupt flag = "0").
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) 6.9 Programmable Timer The control registers of the programmable timer are shown in Table 6.9.1. I/O data memory of the programmable timer Table 6.9.
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) Control of the programmable timer S1C62740 has a programmable timer with OSC1, OSC3 and external K10 input predivided. Input clock selection Input clock may be selected by PTC1 and PTC0 as shown in Table 6.9.2. Table 6.9.
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) Programmable timer control The PTRST bit resets the programmable timer. By writing "1" on PTRST, the programmable timer is reset. The contents set in reload registers RD0–RD7 are loaded into the downcounter. The PTRUN bit controls RUN/STOP of the programmable timer. By writing "1" on PTRUN, the programmable timer performs counting operation. Writing "0" will make the programmable timer stop counting.
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) Overflow signal output Overflow signal of programmable timer is generated to output port R01 if RTR01 is set. This overflow output is toggled when programmable timer completes the down-counting (at the same time reload occurs). PTRST PTRUN Timer data Fig. 6.9.3 Programmable timer overflow output (PTR01 = "1", R01 register = "0") R01 Timer overflow (reload) Note: When R01 output port is set for PTOVF, set R01 to "0".
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) AND MX,1101B ;DISABLE R01 REGISTER OUTPUT LD LD X,ZPTC2 ;SELECT PT INPUT FREQ.
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CHAPTER 6: PERIPHERAL CIRCUITS (Programmable Timer) Programming notes (1) When initiating programmable timer count, perform programming by the following steps: 1. Set the initial data to RD0–RD7. 2. Reset the programmable timer by writing "1" to PTRST. 3. Start the down-count by writing "1" to PTRUN. (2) When the reload register (RD0–RD7) value is set at "00H", the down-counter becomes a 256-value counter. (3) Be sure to data reading in the order of low-order data (PT0–PT3) then high-order data (PT4–PT7).
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) 6.10 Serial Interface Circuit The control registers of the serial interface circuit are shown in Table 6.10.1. I/O data memory of the serial interface circuit Table 6.10.
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) Master/slave mode and synchronous clock (SCLK) The serial interface of the S1C62740 has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock. In the slave mode, the synchronous clock output from the external (master side) serial device is input.
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) The input data will be fetched at the rising edge of SCLK. When the input of the 8 bits data from SD0–SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data.
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) JP SIOINT ;SIO INTERRUPT ROUTINE ; ;* OUTPUT DATA TO SERIAL INTERFACE ;* USE MASTER MODE WITH PROGRAMMABLE TIMER PTOVF ;* INPUT FOR SERIAL SYNCHRONOUS CLOCK OUTSIO: LD X,ZSDL ;RESET SERIAL INTERFACE CIRCUIT LDPX A,MX LD A,MX ; LD X,ZSIOC1 LD MX,1101B ;SET P20-P23 AS SERIAL INTERFACE PORT ;SET LSB FIRST ;SET MASTER MODE AND USE PTOVF FOR ;SERIAL CLOCK LD X,ZRDL ;SET PT RELOAD REGISTER ;(RDH,RDL) = (0,0) LBPX MX,00H ; LD X,ZPTC2 ;SET PT INPUT FREQ.
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) ;* SERIAL INTERRUPT SERVICE ROUTINE SIOINT: LD X,ZISIO ;CHECK SIO INTERRUPT FLAG FAN MX,0001B JP Z,SIOIN1 ; LD X,ZSDL ;READ SERIAL DATA INTO A, B REGISTER LDPX A,MX LD B,MX ; : ; DO THE INTERRUPT SERVICE ROUTINE ; : SIOIN1: EI RET ; ;* INPUT DATA FROM SERIAL INTERFACE ;* USE SLAVE MODE WITH POLLING METHOD RDSIO: LD X,ZSDL LDPX A,MX ;RESET SERIAL INTERFACE CIRCUIT LD A,MX ; LD X,ZSIOC1 ;SELECT SLAVE MODE LD MX,1000B ;SELECT MSB FIRST ;SET P20-P23 AS
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CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit) Programming notes (1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 ↔ fOSC3) while the serial interface is operating. (2) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output).
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CHAPTER 6: PERIPHERAL CIRCUITS (Amplifier) 6.11 Amplifier I/O data memory of the amplifier circuit The control registers of the amplifier circuit are shown in Table 6.11.1. Table 6.11.
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CHAPTER 6: PERIPHERAL CIRCUITS (Amplifier) Example program for the amplifier circuit Following program shows the amplifier controlling procedure. Programming notes (1) It takes about 3 msec for the AMP0 or AMP1 output becomes stable when the circuit is turned on. Therefore, the program must include a wait time of at least 3 msec before the output data is loaded after the AMP1 or AMP0 circuit has been turned on.
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CHAPTER 6: PERIPHERAL CIRCUITS (SVD Circuit) 6.12 SVD (Supply Voltage Detection) Circuit The control registers of the SVD circuit are shown in Table 6.12.1. I/O data memory of the SVD circuit Table 6.12.
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CHAPTER 6: PERIPHERAL CIRCUITS (SVD Circuit) Example program for the SVD circuit Following program shows the SVD controlling procedure. Label Mnemonic/operand ;* ;* SVD (FOR ;* ZSVDC EQU ; SCDCHK: LD LD ; OR AND ; LD RET ; Programming notes Comment OSC1 OPERATION) 0FFH ;SVD CONTROL REGISTER X,ZSVDC MX,0000B ;SET CRITERIA VOLTAGE = 2.
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) 6.13 A/D Converter I/O data memory of A/D converter The control registers of the A/D converter are shown in Table 6.13.1. Table 6.13.
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) Feature of the A/D converter The S1C62740 has a built-in A/D converter with following characteristics: (1) Using dual-slope conversion method (2) Conversion time and resolution can change by software (3) Can measurement different voltage between two inputs, or between one input and GND (4) Can measurement resistor between two inputs (5) Can generate GND signal internally, also GND signal can be support by external circuit (6) A/D converter reference voltage c
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) Measurement mode selection The A/D converter can measurement the following mode: • Terminal voltage vs GND • Difference voltage between terminal • Resistance between terminal How to set the measurement mode and measurement terminals are shown as following: Table 6.13.
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) A/D converter interrupt When the reverse integration period has terminates, the A/D interrupt factor flag IAD is set to "1" and an interrupt occurs. The A/D interrupt can also be masked by writing a "0" into the interrupt mask register EIAD. When EIAD is set to "1", an interrupt occurs.
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) LDPX LBPX MX,0 MX,01H LD X,ZADON OR MX,1000B ; ;RESET A/D CONVERTER, ;AND START A/D CONVERSION ; DI LD LD LD OR EI : : X,ZIAD ;RESET INTERRUPT FLAG A,MX X,ZEIAD ;ENABLE A/D INTERRUPT MX,0100B ; ; ; ;* A/D INTERRUPT SERVICE ROUTINE ADINT: LD X,ZIAD FAN MX,0001B ;CHECK INTERRUPT FLAG = 1 ? JP Z,ADINT1 ;JUMP IF NOT ; LD X,ZAD0 ;READ A/D CONVERTER COUNTER ;TO BUFFER LD Y,DATA0 LDPX MY,MX INC Y LDPX MY,MX INC Y LDPX MY,MX INC Y LDPX MY,MX INC Y LD MY,MX FA
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CHAPTER 6: PERIPHERAL CIRCUITS (A/D Converter) Programming notes (1) To reduce current consumption, set the reference voltage generation circuit, the middle electric potential generation circuit and the A/D converter to OFF when it is not necessary. (2) Do not fail to select the correct combinations for the analog input terminal and measurement items. (Refer to Table 6.13.4) (3) To perform a stable A/D conversion, secure the decided wait time.
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CHAPTER 6: PERIPHERAL CIRCUITS (Sleep) 6.14 Sleep The control registers of the sleep function are shown in Table 6.14.1. I/O data memory of sleep function Table 6.14.
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CHAPTER 6: PERIPHERAL CIRCUITS (Sleep) Use K10 input port to wakeup Example program for the sleep function • Set the proper RAM's data and I/O register's data if necessary. • Set input comparison register (DFK10) to "1" or "0"; Set interrupt mask register EIK1 = "1"; Set interrupt flag (EI). • Executes "SLP" and the chip sleeps. • When K10 input port mismatch to DFK10, then the chip wakeup, and go to K10 interrupt service routine.
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CHAPTER 6: PERIPHERAL CIRCUITS (Sleep) ; LD OR EI X,ZEIK ;ENABLE K10 INTERRUPT MX,0010B ; SLP ; (AFTER K10 INTERRUPT SERVICE FINISH, PROGRAM COUNTER ; WILL COME HERE) ; : ; ;* SYSTEM INITIALIZE ROUTINE INIT: ; : ; DO SOME INITIALIZE PROCEDURE ; : CALL CHKSLP ;CALL CHECK SLEEP ROUTINE JP Z,INIT1 ;JUMP IF WAKEUP FROM SLEEP ; : ; DO NORMAL SYSTEM RESET ROUTINE ; : INIT1: ; ; ; ; ;* K10 K1INT: : DO WAKEUP SERVICE ROUTINE : INTERRUPT SERVICE ROUTINE LD X,ZK1 ;READ INTERRUPT FLAG LD A,MX CALL CHKSLP ;CALL CH
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CHAPTER 6: PERIPHERAL CIRCUITS (Sleep) INC CP LD LBPX CHKSL1: RET ; Programming notes X ;THIS ROUTINE RETURN ;WITH ZERO FLAG = 1 MX,5H ;IF NOT EQUAL THEN ;THIS ROUTINE RETURN ;WITH ZERO FLAG = 0 X,CHDATA ;CLEAR THE SLEEPING FLAG MX,0 (1) Because all I/O registers remain the same values, so please set the proper values before execute "SLP" instruction. (2) After the K10 input port or external system reset trigger to the chip, the chip should wait, then wakeup.
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) 6.15 Interrupt When an interrupt request is issued to the CPU, the CPU starts interrupt processing. Interrupt processing is accomplished by the following steps after the instruction being executed is completed. Interrupt vector, factor flag, and mask register ➀ The address (value of the program counter) of the program which should be run next is saved in the stack area (RAM).
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) IPT EIPT ISIO EISIO K10 IK1 DFK10 SLEEP cancellation EIK1 K00 DFK00 Interrupt vector generation circuit SIK00 K01 Program counter (low-order 4 bits) DFK01 SIK01 IK0 K02 EIK0 DFK02 SIK02 K03 INT (interrupt request) DFK03 SIK03 Interrupt flag IAD EIAD ISW1 EISW1 ISW0 Interrupt factor flag EISW0 Interrupt mask register IT1 EIT1 Input comparison register IT2 Interrupt selection register EIT2 IT8 EIT8 IT32 EIT32 Fig. 6.15.
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) Table 6.15.
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) ; ORG JP 10CH SIOINT ORG JP 10EH PTINT ;SIO (2nd PRIORITY) ; ;PTM (1st PRIORITY) ; ;* APPLICATION MAIN ROUTINE MAIN: DI ; : ; (ENABLE TIMER.
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) CHKSW0: FAN B,0001B ;CHECK STOPWATCH 1/10 Hz ;INTERRUPT FLAG Z,CHKSW1 ;NO, THEN JUMP SERSW0 ;STOPWATCH 1/10 Hz SERVICE ROUTINE JP CALL CHKSW1: FAN B,0010B ;CHECK STOPWATCH 1 Hz INTERRUPT FLAG JP Z,INTEND ;NO, THEN JUMP CALL SERSW1 ;STOPWATCH 1 Hz SERVICE ROUTINE JP INTEND ; ;* A/D CONVERTER INTERRUPT ADINT: LD X,ZIAD ;CHECK A/D INTERRUPT FLAG FAN MX,0001B JP Z,INTEND ;NO, THEN JUMP CALL SERAD ;A/D SERVICE ROUTINE JP INTEND ; ;* K0 INTERRUPT SERVICE ROUTINE K0IN
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) ; ; ; DO THE TIMER 32 Hz INTERRUPT SERVICE ROUTINE HERE : RET ; SERT8: ; : ; DO THE TIMER 8 Hz INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERT2: ; : ; DO THE TIMER 2 Hz INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERT1: ; : ; DO THE TIMER 1 Hz INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERSW0: ; : ; DO THE STOPWATCH 1/10 Hz INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERSW1: ; : ; DO THE STOPWATCH 1 Hz INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERAD: ; : ; DO THE
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CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt) ; SERK1: ; : ; DO THE INPUT K1 INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERSIO: ; : ; DO THE SIO INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; SERPT: ; : ; DO THE PROGRAMMABLE TIMER INTERRUPT ; SERVICE ROUTINE HERE ; : RET ; Programming notes (1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting of the interrupt mask register. (2) Read the interrupt factor flag in the DI status (interrupt flag = "0").
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CHAPTER 7: SUMMARY OF NOTES CHAPTER 7 SUMMARY OF NOTES 7.1 Notes for Low Current Consumption The S1C62740 contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 7.1.
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CHAPTER 7: SUMMARY OF NOTES 7.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. System initialization In some of initial registers and initial data memory area, the initial value is undefined after reset. Set them proper initial values by the program, as necessary. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual.
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CHAPTER 7: SUMMARY OF NOTES (2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. (3) To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. (4) When shifting to the SLEEP status, the CPU clock must be set to OSC1 and the OSC3 oscillation circuit must be OFF.
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CHAPTER 7: SUMMARY OF NOTES Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull up registance 300 kΩ LCD driver (1) The contents of the display memory are undefined until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing.
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CHAPTER 7: SUMMARY OF NOTES Serial interface (1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 ↔ fOSC3) while the serial interface is operating. (2) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output).
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CHAPTER 7: SUMMARY OF NOTES (5) When reading data after turning the A/D converter OFF, the A/ D converter should be OFF in the period from an interrupt generation to the beginning of a reverse integration. (6) When the A/D converter is reset or turned OFF, the interrupt factor flag (IAD) may sometimes be set to "1". Consequently, read the flag (reset the flag) as necessary at reset or at the turning OFF.
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APPENDIX A: S1C62740 DATA MEMORY (RAM) MAP A APPENDIX S1C62740 DATA MEMORY (RAM) MAP II-82 EPSON LSB LSB NAME MSB 7 LSB NAME MSB 6 LSB NAME MSB 5 LSB NAME MSB 4 LSB NAME MSB 3 LSB NAME MSB 2 1 LSB NAME MSB 0 L NAME MSB P H 0 0 PROGRAM NAME: 1 2 3 4 5 6 7 8 9 A B C D E F RAM map - 1 (000H–07FH) S1C62740 TECHNICAL SOFTWARE
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S1C62740 TECHNICAL SOFTWARE EPSON 7 6 5 4 3 2 1 P H 1 0 LSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB NAME MSB L 0 PROGRAM NAME: 1 2 3 4 5 6 7 8 9 A B C D E F APPENDIX A: S1C62740 DATA MEMORY (RAM) MAP RAM map - 2 (100H–17FH) II-83
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II-84 EPSON 7 6 5 4 3 2 1 P H 2 0 LSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB NAME MSB L 0 PROGRAM NAME: 1 2 3 4 5 6 7 8 9 A B C D E F APPENDIX A: S1C62740 DATA MEMORY (RAM) MAP RAM map - 3 (200H–27FH) S1C62740 TECHNICAL SOFTWARE
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S1C62740 TECHNICAL SOFTWARE EPSON 7 6 5 4 3 2 1 P H 3 0 LSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB NAME MSB L 0 PROGRAM NAME: 1 2 3 4 5 6 7 8 9 A B C D E F APPENDIX A: S1C62740 DATA MEMORY (RAM) MAP RAM map - 4 (300H–37FH) II-85
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II-86 EPSON F E D C 3 9 2 1 P H 0 8 LSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB LSB NAME MSB NAME MSB L 1 2 ZIK1 ZISIO ZIPT 0 0 0 0 0 0 0 0 0 IK1 ISIO IPT ZDFK0 ZK1 ZK0 DFK03 0 K03 DFK02 0 K02 DFK01 0 K01 DFK00 K10 K00 ZBZCTL ZFOCTL ZTMRST 0 BZR03 FOR00 0 0 BZR02 0 FOFQ1 0 BZFQ FOFQ0 TMRST ZGNDON ZAMPON ZAMPDT 0 0 GNDON1 0 0 GNDON0 VRAON AMPON1 AMPDT1 VRON AMPON0 AMPDT0 0 PROGRAM NAME: ZIK0 0 0 0 IK0 ZDFK1 0 0 0 DFK10 ZTML TM3 TM2 TM1 TM0 ZADRS 0 0 ADRS1 ADRS0 3 ZIAD 0 0
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APPENDIX B: S1C62740 INSTRUCTION SET B APPENDIX S1C62740 INSTRUCTION SET Instruction set - 1 Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP ← p4, NPP ← p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 if C=0 Z, s 0
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APPENDIX B: S1C62740 INSTRUCTION SET Instruction set - 2 Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r ← i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q
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APPENDIX B: S1C62740 INSTRUCTION SET Instruction set - 3 Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH← M(SP), SP ← SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL ← M(SP), SP ← SP+1 instructions F ↑ ↓ ↑ ↑ 1 1 1 1 1 1 0 1 1 0 1 0 ↓ ↑ ↓ ↓ 5 F ← M(SP), SP ← SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH ← r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL ← r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r ← SPH r, SPL
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APPENDIX B: S1C62740 INSTRUCTION SET Abbreviations used in the explanations have the following meanings. Symbols associated with A ................ A register registers and memory B ................ B register X ................ XHL register (low order eight bits of index register IX) Y ................ YHL register (low order eight bits of index register IY) XH ............. XH register (high order four bits of XHL register) XL .............. XL register (low order four bits of XHL register) YH .........
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APPENDIX B: S1C62740 INSTRUCTION SET Symbols associated with NBP ....... New bank pointer program counter NPP ....... New page pointer PCB ....... Program counter bank PCP ....... Program counter page PCS ....... Program counter step PCSH .... Four high order bits of PCS PCSL ..... Four low order bits of PCS Symbols associated with F ........... Flag register (I, D, Z, C) flags C ........... Carry flag Z ........... Zero flag D ........... Decimal flag I ............ Interrupt flag ↓ ...............
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APPENDIX C: PSEUDO-INSTRUCTION TABLE OF THE CROSS ASSEMBLER APPENDIX C Item No.
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APPENDIX D: COMMAND TABLE OF ICE D APPENDIX COMMAND TABLE OF ICE ICE command table - 1 Item No.
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APPENDIX D: COMMAND TABLE OF ICE ICE command table - 2 Item No.
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