Specifications

26 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.7.3 I/O memory of clock timer
Table 4.7.3.1 shows the clock timer control bits and their addresses.
Table 4.7.3.1 Control bits of clock timer
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
0EBH
0 EIT2 EIT8 EIT32
RR/W
0
∗ 3
EIT2
EIT8
EIT32
–
∗ 2
0
0
0
–
Enable
Enable
Enable
–
Mask
Mask
Mask
Unused
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0EFH
0 IT2 IT8 IT32
R
0
∗ 3
IT2
∗ 4
IT8
∗ 4
IT32
∗ 4
–
∗ 2
0
0
0
–
Yes
Yes
Yes
–
No
No
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
∗1
∗2
Initial value at initial reset
Not set in the circuit
∗3
∗4
Always "0" being read
Reset (0) immediately after being read
0F9H
0 TMRST 0 0
RW R
0
∗ 3
TMRST
∗ 3
0
∗ 3
0
∗ 3
–
∗ 2
Reset
–
∗ 2
–
∗ 2
–
Reset
–
–
–
–
–
–
Unused
Clock timer reset
Unused
Unused
TM0–TM3: Timer data (0E4H)
The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-
only, and write operations are invalid.
At initial reset, the timer data is initialized to "0H".
EIT32, EIT8, EIT2: Interrupt mask registers (0EBH•D0–D2)
These registers are used to mask the clock timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading: Valid
The interrupt mask registers (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8
Hz, 2 Hz).
At initial reset, these registers are all set to 0.
IT32, IT8, IT2: Interrupt factor flags (0EFH•D0–D2)
These flags indicate the status of the clock timer interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The
software can determine from these flags whether there is a clock timer interrupt. However, even if the
interrupt is masked, the flags are set to 1 at the falling edge of the signal. These flags can be reset when
the register is read by the software.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated. Be very careful when interrupt factor flags are in the same address.
At initial reset, these flags are set to 0.